View XRT83SH380609_1506938.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xrt83sh38 8-channel t1/e1/j1 short-haul line interface unit september 2006 rev. 1.0.7 general description the xrt83sh38 is a fully integrated 8-channel short- haul line interface unit (liu) that operates from a single 3.3v power supply. using internal termination, the liu provides one bill of materials to operate in t1, e1, or j1 mode with minimum external components. the liu features are programmed through a standard microprocessor interface, serial interface or controlled through hardware mode. exar?s liu has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the liu is powered off. key design features within the liu optimize 1:1 or 1+1 redundancy and non-intrusive monitoring applications to ensure reliability without using relays. the on-chip clock synthesi zer generates t1/e1/j1 clock rates from a selectab le external clock frequency and outputs a clock reference of the line rate chosen. additional features include rlos, a 16-bit lcv counter for each channel, ais, qrss generation/ detection, taos, dmo, and diagnostic loopback modes. applications ? t1 digital cross-connects (dsx-1) ? isdn primary rate interface ? csu/dsu e1/t1/j1 interface ? t1/e1/j1 lan/wan routers ? public switching syst ems and pbx interfaces ? t1/e1/j1 multiplexer and channel banks f igure 1. b lock d iagram of the xrt83sh38 t1/e1/j1 liu (h ost m ode ) 1 of 8 channels, channel_n hw/host wr_r/w rd_ds ale-as cs rdy_dtack/sdo int ser_par ict tpos_n/tdata_n tneg_n/codes_n tclk_n rclk_n rneg_n/lcv_n rpos_n/rdata_n rlos_n rring_n master clock synthesizer qrss pattern generator dmo_n ttip_n tring_n txon_n hdb3/ b8zs encoder tx/rx jitter attenuator timing control tx filter & pulse shaper line driver drive monitor hdb3/ b8zs decoder tx/rx jitter attenuator timing & data recovery peak detector & slicer qrss detector ais detector los detector pts1 pts2 d[7:0] pclk/sclk a[7:0]/sdi reset microprocessor/serial interface controller test mclke1 mclkt1 mclkout taos rtip_n remote loopback digital loopback analog loopback
xrt83sh38 2 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 f igure 2. b lock d iagram of the xrt83sh38 t1/e1/j1 liu (h ardware m ode ) 1 of 8 channels, channel_n qrss pattern generator hdb3/ b8zs encoder tx/rx jitter attenuator timing control tx filter & pulse shaper line driver drive monitor hdb3/ b8zs decoder tx/rx jitter attenuator timing & data recovery peak detector & slicer qrss detector ais detector los detector taos remote loopback digital loopback analog loopback hw/host gauge jasel1 jasel0 rxtsel txtsel terselr xres0 rxres1 ict mclke1 mclkt1 clksel[2:0] tpos_n/tdata_n tneg_n/codes_n tclk_n rclk_n rneg_n/lcv_n rpos_n/rdata_n rlos_n rtip_n rring_n master clock synthesizer dmo_n ttip_n tring_n txon_n harware control test reset tratio sr/dr eqc[4:0] tclke rclke rxmute ataos mclkout taos_n loop1_n loop0_n
xrt83sh38 3 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit features ? fully integrated eight channel short-haul tr ansceivers for e1,t1 or j1 applications ? programable transmit pulse shaper for e1,t1 or j1 short-haul interfaces ? five fixed transmit pulse settings for t1 short-haul applications ? receive monitor mode handles 0 to 29db resistive at tenuation along with 0 to 6db of cable attenuation for e1 and 0 to 3db of cable attenuation for t1 modes ? internal impedance matching for 75 ? , 100 ?, 110 ? and 120 ? ? tri-state transmit ou tput and receive input capab ility for redundanc y applications ? provides high impedance for tx and rx during power off ? transmit return loss meets or exceeds etsi 300-166 standard ? on-chip digital clock recovery circuit for high input jitter tolerance ? crystal-less digital jitter attenuator with 32-bit or 64-bit fifo selectable either in transmit or receive path ? on-chip frequency multiplier generates t1 or e1 master clocks from variety of external clock sources ? high receiver inte rference immunity ? on-chip transmit short-circuit protection and limiting, and driver fa il monitor output (dmo) ? receive loss of signal (rlos) output ? on-chip hdb3/b8zs/ami encoder/decoder functions ? qrss pattern generator and detection for testing and monitoring ? error and bipolar violation insertion and detection ? transmit all ones (taos) generators and detectors ? supports local analog, remote, digital and dual loop-back modes ? meets or exceeds t1 and e1 short-haul network access specifications in itu g.703, g.775, g.736 and g.823; tr-tsy-000499; ansi t1.403 and t1.408; etsi 300-166 and at&t pub 62411 ? supports both hardware and host (parallel microprocessor or serial) interface for programming ? jtag support ? programmable interrupt ? low power dissipation ? logic inputs accept either 3.3v or 5v levels ? single 3.3v supply operation ? 225 ball bga package ? -40c to +85c temperature range ordering information p art n umber p ackage o perating t emperature r ange xrt83sh38ib 225 ball bga -40 c to +85 c
xrt83sh38 4 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 nc4 nc12 rtip_3 rring_3 nc11 rring_2 rtip_2 rneg_2 gauge dvddd_p rtip_6 rring_6 nc10 nc9 rring_7 rtip_7 rvdd_7 nc3 18 rclk_3 rpos_3 tgnd_3 rgnd_3 tvdd_3 ttip_2 rgnd_2 dgnd_p agnd_bias avdd_bias rpos_6 rgnd_6 rvdd_6 tring_7 rgnd_7 rpos_7 dmo_6 rneg_7 17 rlos_3 rneg_3 ttip_3 rvddd_3 tring_3 tvdd_2 rvdd_2 rclk_2 pts1 rxon int rneg_6 ttip_6 ttip_7 tgnd_7 tgnd_6 rclk_7 tclk_6 16 tclk_2 tneg_3 dmo_2 rpos_2 tgnd_2 tring_2 dgnd_dr rlos_2 rlos_6 dvdd_dr pts2 rclk_6 tvdd_6 tvdd_7 tring_6 rlos_7 tclk_7 tpos_6 15 jasel0 tpos_2 tclk_3 tpos_3 xrt83sh38 (top view) 225 ball bga tneg_7 tpos_7 tneg_6 dmo_7 14 txon_0 jasel1 dmo_3 tneg_2 txon_7 pclk txon_5 txon_4 13 a[7] tx0n_3 txon_2 txon_1 txon_6 rxmute test ict 12 a[3] a[6] a[5] a[4] tersel0 tersel1 rxtsel txtsel 11 a[1] a[2] a[0] dvdd_pdr rxres1 hw_ host dvdd_pdr rxres0 10 dvdd dgnd dgnd_pdr dvdd_dr dvdd_dr dgnd_dr d[1] d[3] 9 clksel0 clksel1 clksel2 dgnd_dr dgnd_pdr reset d[2] d[4] 8 ale_ as cs rd _ ds wr _r/ w d[0] d[7] d[6] d[5] 7 rdy_ dtack taos_1 taos_3 taos_0 taos_7 taos_4 taos_5 taos_6 6 taos_2 tneg_1 tpos_0 dmo_0 rvdd_1 dmo_4 tclk_5 tpos_5 tneg_5 5 tpos_1 tclk_0 tneg_0 dmo_1 tvdd_0 tvdd_1 ttip_1 rlos_1 dvdd_dr sr_ dr gndpll_2 rneg_5 tring_5 dmo_5 tvdd_4 rneg_4 tneg_4 tpos_4 4 tclk_1 rclk_0 rlos_0 tgnd_0 ttip_0 tring_1 rgnd_1 rclk_1 vddpll_1 gndpll_1 rclk_5 rpos_5 rvdd_5 tgnd_5 tgnd_4 tclk_4 rclk_4 rlos_4 3 rneg_0 rpos_0 rvdd_0 rgnd_0 tring_o tgnd_1 rpos_1 rneg_1 vddpll_2 dgnd_dr rlos_5 rgnd_5 ttip_5 tring_4 ttip_4 rgnd_4 rpos_4 rvdd_4 2 nc1 nc5 rtip_0 rring_0 nc6 rring_1 rtip_1 mclkout mclke1 mclkt1 rtip_5 rring_5 nc7 tvdd_5 nc8 rring_4 rtip_4 nc2 1 a b c d e f g h j k l m n p r t u v
xrt83sh38 i rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit table of contents general description............................................................................................................ .. 1 a pplications ............................................................................................................................... ................................ 1 f igure 1. b lock d iagram of the xrt83sh38 t1/e1/j1 liu (h ost m ode )....................................................................................... 1 f igure 2. b lock d iagram of the xrt83sh38 t1/e1/j1 liu (h ardware m ode ) .............................................................................. 2 f eatures ............................................................................................................................... ...................................... 3 ordering information ........................................................................................................... ......... 3 pin description by function............................................................................................... 5 r eceive s ection ............................................................................................................................... .......................... 5 t ransmit s ection ............................................................................................................................... ........................ 8 m icroprocessor i nterface ............................................................................................................................... ..... 10 jitter a ttenuator ............................................................................................................................... ..................... 12 c lock s ynthesizer ............................................................................................................................... ................... 12 a larm f unctions /r edundancy s upport ................................................................................................................. 14 s erial p ort and jtag ............................................................................................................................... ................ 16 p ower and g round ............................................................................................................................... ................... 17 functional description .... .......................................... ........................................... ............. 19 1.0 hardware mode vs host mode .............................................................................................. .. 19 1.1 feature differences in hardw are mode ........... .............. .............. ........... ........... ........... ............ .. 19 t able 1: d ifferences b etween h ardware m ode and h ost m ode ................................................................................................. 19 2.0 master clock generator .................................................................................................. ....... 20 f igure 3. t wo i nput c lock s ource ............................................................................................................................... .................. 20 f igure 4. o ne i nput c lock s ource ............................................................................................................................... .................. 20 t able 2: m aster c lock g enerator ............................................................................................................................... .................. 20 3.0 receive path line interface ............................................................................................. ....... 21 f igure 5. s implified b lock d iagram of the r eceive p ath ............................................................................................................ 21 3.1 line termination (rtip/rring) ........................................................................................... ................... 21 3.1.1 case 1: internal termination........................................................................................... ............................... 21 t able 3: s electing the i nternal i mpedance ............................................................................................................................... .... 21 f igure 6. t ypical c onnection d iagram u sing i nternal t ermination .......................................................................................... 22 3.1.2 case 2: internal termination with one external fixed resistor for all modes .................... 22 t able 4: s electing the v alue of the e xternal f ixed r esistor .................................................................................................... 22 f igure 7. t ypical c onnection d iagram u sing o ne e xternal f ixed r esistor ............................................................................. 22 3.2 clock and data recovery ................................................................................................. .................. 22 f igure 8. r eceive d ata u pdated on the r ising e dge of rclk..................................................................................................... 23 f igure 9. r eceive d ata u pdated on the f alling e dge of rclk................................................................................................... 23 t able 5: t iming s pecifications for rclk/rpos/rneg ................................................................................................................ 23 3.2.1 receive sensitivity .................................................................................................... .......................................... 23 f igure 10. t est c onfiguration for m easuring r eceive s ensitivity ............................................................................................ 24 3.2.2 interference margin .................................................................................................... ..................................... 24 f igure 11. t est c onfiguration for m easuring i nterference m argin ......................................................................................... 24 3.2.3 general alarm detection and interrupt generation ....................................................................... . 24 3.2.3.1 rlos (r eceiver l oss of s ignal ) ..................................................................................................................... 24 f igure 12. a nalog r eceive l os of s ignal for t1/e1/j1................................................................................................................ 25 t able 6: a nalog rlos d eclare /c lear (t ypical v alues ) for t1/e1 ............................................................................................. 25 3.2.3.2 exlos (e xtended l oss of s ignal ) ................................................................................................................. 25 3.2.3.3 ais (a larm i ndication s ignal ) ......................................................................................................................... 25 3.2.3.4 flsd (fifo l imit s tatus d etection ) ............................................................................................................... 25 3.2.3.5 lcvd (l ine c ode v iolation d etection ) ........................................................................................................... 25 3.3 receive jitter attenuator ............. .............. .............. .............. .............. .............. ............ ................... 26 3.4 hdb3/b8zs decoder ............. .............. .............. .............. .............. .............. ........... ......... ........................... 26 3.5 rpos/rneg/rclk .......................................................................................................... .............................. 26 f igure 13. s ingle r ail m ode w ith a f ixed r epeating "0011" p attern ......................................................................................... 26 f igure 14. d ual r ail m ode w ith a f ixed r epeating "0011" p attern ............................................................................................ 26 3.6 rxmute (receiver los with data muting) ...... ............................................................................ ..... 27 f igure 15. s implified b lock d iagram of the r x mute f unction ................................................................................................... 27 4.0 transmit path line interface ............................................................................................ ..... 28 f igure 16. s implified b lock d iagram of the t ransmit p ath ......................................................................................................... 28 4.1 tclk/tpos/tneg digital inputs ........................................................................................... ................. 28 f igure 17. t ransmit d ata s ampled on f alling e dge of tclk...................................................................................................... 28 f igure 18. t ransmit d ata s ampled on r ising e dge of tclk........................................................................................................ 28
xrt83sh38 ii 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 t able 7: t iming s pecifications for tclk/tpos/tneg................................................................................................................ .. 29 4.2 hdb3/b8zs encoder .............. .............. .............. .............. .............. ........... ........... ........... ........................... 29 t able 8: e xamples of hdb3 e ncoding ............................................................................................................................... ............. 29 t able 9: e xamples of b8zs e ncoding ............................................................................................................................... .............. 29 4.3 transmit jitter attenuator .............................................................................................. ................. 30 t able 10: m aximum g ap w idth for m ultiplexer /m apper a pplications ......................................................................................... 30 4.4 taos (transmit all ones) ................................................................................................ ...................... 30 f igure 19. taos (t ransmit a ll o nes ) .............................................................................................................................. .............. 30 4.5 transmit diagnostic features ............................................................................................ .............. 30 4.5.1 ataos (automatic transmit all ones).................................................................................... ..................... 31 f igure 20. s implified b lock d iagram of the ataos f unction ..................................................................................................... 31 4.5.2 qrss generation........................................................................................................ .......................................... 31 t able 11: r andom b it s equence p olynomials ............................................................................................................................... .31 4.5.3 t1 short haul line build out (lbo) ..................................................................................... .......................... 31 t able 12: s hort h aul l ine b uild o ut ............................................................................................................................... ............... 31 4.5.4 arbitrary pulse generator for t1 and e1 ................................................................................ ............... 32 f igure 21. a rbitrary p ulse s egment a ssignment ......................................................................................................................... 32 4.6 dmo (digital monitor output) ............................................................................................ ................. 32 4.7 line termination (ttip/tring) ........................................................................................... .................... 33 f igure 22. t ypical c onnection d iagram u sing i nternal t ermination ......................................................................................... 33 5.0 t1/e1 applications ...................................................................................................... ...................34 5.1 loopback diagnostic s .............. .............. .............. .............. ............ ........... ........... .......... ...................... 34 5.1.1 local analog loopback .................................................................................................. ................................ 34 f igure 23. s implified b lock d iagram of l ocal a nalog l oopback ................................................................................................ 34 5.1.2 remote loopback ........................................................................................................ ........................................ 34 f igure 24. s implified b lock d iagram of r emote l oopback .......................................................................................................... 34 5.1.3 digital loopback ....................................................................................................... .......................................... 35 f igure 25. s implified b lock d iagram of d igital l oopback ........................................................................................................... 35 5.1.4 dual loopback .......................................................................................................... ........................................... 35 f igure 26. s implified b lock d iagram of d ual l oopback ............................................................................................................... 35 5.2 line card redundancy ............. .............. .............. .............. .............. ........... ........... ......... ....................... 36 5.2.1 1:1 and 1+1 redundancy without relays .................................................................................. .................. 36 5.2.2 transmit interface with 1:1 and 1+1 redundancy ......................................................................... ......... 36 f igure 27. s implified b lock d iagram of the t ransmit i nterface for 1:1 and 1+1 r edundancy ................................................ 36 5.2.3 receive interface with 1:1 and 1+1 redundancy.......................................................................... ........... 37 f igure 28. s implified b lock d iagram of the r eceive i nterface for 1:1 and 1+1 r edundancy .................................................. 37 5.2.4 n+1 redundancy using external relays ................................................................................... ................ 38 5.2.5 transmit interface with n+1 redundancy ................................................................................. ............... 38 f igure 29. s implified b lock d iagram of the t ransmit i nterface for n+1 r edundancy ............................................................ 38 5.2.6 receive interface with n+1 redundancy .................................................................................. ................. 39 f igure 30. s implified b lock d iagram of the r eceive i nterface for n+1 r edundancy .............................................................. 39 5.3 power failure protection ................................................................................................ .................. 40 5.4 overvoltage and overcurrent pr otection ..... .............. .............. .............. .............. ........... ....... 40 5.5 non-intrusive monitoring ................................................................................................ .................... 40 f igure 31. s implified b lock d iagram of a n on -i ntrusive m onitoring a pplication ..................................................................... 40 6.0 microprocessor interface ............... ................ ................ ............. ............. ............. .......... ......41 6.1 serial microprocessor interface block ....... .............. .............. .............. ........... ............ ........... . 41 f igure 32. s implified b lock d iagram of the s erial m icroprocessor i nterface ........................................................................ 41 6.1.1 serial timing information.............................................................................................. .................................. 41 f igure 33. t iming d iagram for the s erial m icroprocessor i nterface ....................................................................................... 41 6.1.2 24-bit serial data input descritption .................................................................................. ....................... 42 6.1.3 addr[7:0] (sclk1 - sclk8) .............................................................................................. ....................................... 42 6.1.4 r/w (sclk9)............................................................................................................ ................................................... 42 6.1.5 dummy bits (sclk10 - sclk16) ........................................................................................... ................................. 42 6.1.6 data[7:0] (sclk17 - sclk24) ............................................................................................ ..................................... 42 6.1.7 8-bit serial data output description ................................................................................... ...................... 42 f igure 34. t iming d iagram for the m icroprocessor s erial i nterface ....................................................................................... 43 t able 13: m icroprocessor s erial i nterface t imings ( ta = 250c, vdd=3.3v 5% and load = 10 p f) ...................................... 43 6.2 parallel microprocessor interface block .......... .............. .............. ........... ........... ........... ....... 44 t able 14: s electing the m icroprocessor i nterface m ode .......................................................................................................... 44 f igure 35. s implified b lock d iagram of the m icroprocessor i nterface b lock ........................................................................ 44 6.3 the microprocessor in terface block signals ..... .............. .............. ........... ........... ........... ....... 45 t able 15: xrt83sh38 m icroprocessor i nterface s ignals that exhibit constant roles in both i ntel and m otorola m odes 45 t able 16: i ntel mode : m icroprocessor i nterface s ignals ........................................................................................................... 45 t able 17: m otorola m ode : m icroprocessor i nterface s ignals ................................................................................................. 46
xrt83sh38 iii rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit 6.4 intel mode programmed i/o access (asynchronous) ............ .............. .............. .............. ........ 47 f igure 36. i ntel p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations .................................................. 48 t able 18: i ntel m icroprocessor i nterface t iming s pecifications .............................................................................................. 48 6.5 motorola mode programmed i/o access (asynchronous) ............. ........... ............ ........... ..... 49 f igure 37. m otorola 68k p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations .................................. 50 t able 19: m otorola 68k m icroprocessor i nterface t iming s pecifications .............................................................................. 50 register information .......................................................................................................... 5 1 t able 20: m icroprocessor r egister a ddress (addr[7:0]) .......................................................................................................... 51 t able 21: m icroprocessor r egister c hannel d escription ......................................................................................................... 51 t able 22: m icroprocessor r egister 0 x 00 h b it d escription ........................................................................................................ 53 t able 23: e qualizer c ontrol and t ransmit l ine b uild o ut .......................................................................................................... 54 t able 24: m icroprocessor r egister 0 x 01 h b it d escription ........................................................................................................ 54 t able 25: m icroprocessor r egister 0 x 02 h b it d escription ........................................................................................................ 55 t able 26: m icroprocessor r egister 0 x 03 h b it d escription ........................................................................................................ 56 t able 27: m icroprocessor r egister 0 x 04 h b it d escription ........................................................................................................ 57 t able 28: m icroprocessor r egister 0 x 05 h b it d escription ........................................................................................................ 58 t able 29: m icroprocessor r egister 0 x 06 h b it d escription ........................................................................................................ 59 t able 30: m icroprocessor r egister 0 x 08 h b it d escription ........................................................................................................ 60 t able 31: m icroprocessor r egister 0 x 09 h b it d escription ........................................................................................................ 60 t able 32: m icroprocessor r egister 0 x 0a h b it d escription ....................................................................................................... 61 t able 33: m icroprocessor r egister 0 x 0b h b it d escription ....................................................................................................... 61 t able 34: m icroprocessor r egister 0 x 0c h b it d escription ....................................................................................................... 61 t able 35: m icroprocessor r egister 0 x 0d h b it d escription ....................................................................................................... 61 t able 36: m icroprocessor r egister 0 x 0e h b it d escription ....................................................................................................... 62 t able 37: m icroprocessor r egister 0 x 0f h b it d escription ........................................................................................................ 62 t able 38: m icroprocessor r egister 0 x 80 h , b it d escription ....................................................................................................... 63 clock select register ............................................................................................................................... .............. 64 f igure 38. r egister 0 x 81 h s ub r egisters ............................................................................................................................... ...... 64 t able 39: m icroprocessor r egister 0 x 81 h , b it d escription ....................................................................................................... 65 t able 40: m icroprocessor r egister 0 x 82 h b it d escription ........................................................................................................ 66 t able 41: m icroprocessor r egister 0 x 8c h b it d escription ....................................................................................................... 67 t able 42: m icroprocessor r egister 0 x 8d h b it d escription ....................................................................................................... 67 t able 43: m icroprocessor r egister 0 x 8e h b it d escription ....................................................................................................... 68 t able 44: m icroprocessor r egister 0 x c0 h b it d escription ....................................................................................................... 69 t able 45: m icroprocessor r egister 0 x fe h b it d escription ....................................................................................................... 69 t able 46: m icroprocessor r egister 0 x ff h b it d escription ....................................................................................................... 69 electrical characteristic s................................................ ............................................. 70 t able 47: a bsolute m aximum r atings ............................................................................................................................... .............. 70 t able 48: dc d igital i nput and o utput e lectrical c haracteristics ........................................................................................... 70 t able 49: ac e lectrical c haracteristics ............................................................................................................................... ....... 70 t able 50: p ower c onsumption ............................................................................................................................... ......................... 71 t able 51: e1 r eceiver e lectrical c haracteristics ...................................................................................................................... 71 t able 52: t1 r eceiver e lectrical c haracteristics ...................................................................................................................... 72 t able 53: e1 t ransmitter e lectrical c haracteristics ................................................................................................................ 73 t able 54: t1 t ransmitter e lectrical c haracteristics ................................................................................................................. 73 package dimensions ............................................................................................................. 74 ordering information ........................................................................................................... .......................... 75 revisions ...................................................................................................................... ......................................... 75
xrt83sh38 5 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 pin description by function receive section s ignal n ame bga l ead # t ype d escription rxon k16 i receiver on hardware mode only this pin is used to enable the receivers fo r all channels. by default, the receivers are turned on in hardware mode. to turn the receivers off, this "low". n ote : internally pulled "high" with 50k ? resistor. rlos0 rlos1 rlos2 rlos3 rlos4 rlos5 rlos6 rlos7 c3 h4 h15 a16 v3 l2 j15 t15 o receive loss of signal when a receive loss of signal occurs accord ing to itu-t g.775, the rlos pin will go "high" for a minimum of one rclk cycle. rlos will remain "high" until the loss of signal condition clears. see the receive loss of signal section of this datasheet for more details. n ote : this pin can be used for redundancy applications to initiate an automatic switch to a backup card. rclk0 rclk1 rclk2 rclk3 rclk4 rclk5 rclk6 rclk7 b3 h3 h16 a17 u3 l3 m15 u16 o receive clock output rclk is the recovered clock from the incoming data stream. if the incoming signal is absent or rtip/rring are in "high- z", rclk maintains its timing by using an internal master clock as its reference. rpos/rneg data can be updated on either edge of rclk selected by rclke. n ote : rclke is a global setting that applies to all 8 channels. rneg/lcv0 rneg/lcv1 rneg/lcv2 rneg/lcv3 rneg/lcv4 rneg/lcv5 rneg/lcv6 rneg/lcv7 a2 h2 h18 b16 t4 m4 m16 v17 o rneg/lcv_of output in dual rail mode, this pin is the receive negative data output. in single rail mode, this pin is a line code violation / counter overflow indicator. if lcv is selected by programming the appropriate global register and if a line code violation, a bi-polar violation, or excessive zeros occur, the lcv pin will pull "high" for a minimum of one rclk cycle. lcv will remain "high" until ther e are no more violations. however, if of (overflow) is selected the lcv pin will pull "high" if the internal lcv counter is saturated. the lcv pin will remain "high" until the lcv counter is reset. rpos0 rpos1 rpos2 rpos3 rpos4 rpos5 rpos6 rpos7 b2 g2 d15 b17 u2 m3 l17 t17 o rpos/rdata output receive digital output pin. in dual rail mode, this pin is the receive positive data out - put. in single rail mode, this pin is the receive non-return to zero (nrz) data output.
xrt83sh38 6 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit rtip0 rtip1 rtip2 rtip3 rtip4 rtip5 rtip6 rtip7 c1 g1 g18 c18 u1 l1 l18 t18 i receive differential tip input rtip is the positive differential input from the line interface. along with the rring signal, these pins should be coupled to a 1:1 transformer for proper operation. rring0 rring1 rring2 rring3 rring4 rring5 rring6 rring7 d1 f1 f18 d18 t1 m1 m18 r18 i receive differential ring input rring is the negative differential input from the line interface. along with the rtip signal, these pins should be coupled to a 1:1 transformer for proper operation. rxmute t12 i receive data muting hardware mode only this pin is and-ed with each of the rlos functions on a per channel basis. there - fore, if this pin is pulled "high" and a giv en channel experiences a loss of signal, then the rpos/rneg output pins ar e automatically pulled "low" to prevent data chatter - ing. to disable this feature, th e rxmute pin must be pulled "low". n ote : this pin is internally pulled ?high? with a 50k ? resistor s ignal n ame bga l ead # t ype d escription
xrt83sh38 7 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 rxres1 rxres0 r10 v10 i receive external resistor control pins hardware mode only these pins are used in the receive internal impedance mode for unique applica - tions where an accurate resistor can be used to achieve optimal return loss. when rxres[1:0] are used, the li u automatically sets the internal impedance to match the line build out. for example: if 240 ? is selected, the liu chooses an internal impedance such that the parallel combin ation equals the impedance chosen by tersel[1:0]. "00" = no external fixed resistor "01" = 240 ? "10" = 210 ? "11" = 150 ? n ote : these pins are internally pulled ?low? with a 50k ? resistor. this feature is available in host mode by programming the appropriate channel register. rclke/ pts1 j16 i receive clock edge hardware mode this pin is used to select which edge of the recovered clock is used to update data to the receiver on the rpos/rneg outputs. by default, data is updated on the risinge edge. to udpdate data on the falling edge, this pin must be pulled "high". host mode pts[2:1] pins are used to select the type of microprocessor to be used for host communication. "00" = 8051 intel asynchronous "01" = 68k motorola asynchronous "10" = x86 intel synchronous "11" = 860 motorola synchronous n ote : this pin is internally pulled ?low? with a 50k ? resistor. s ignal n ame bga l ead # t ype d escription
xrt83sh38 8 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit transmit section s ignal n ame bga l ead # t ype d escription tclke/pts2 l15 i transmit clock edge hardware mode this pin is used to select which edge of the transmit clock is used to sample data on the transmitter on the tpos/tneg inputs. by default, data is sampled on the falling edge. to sample data on the rising edge, this pin must be pulled "high". host mode pts[2:1] pins are used to select the ty pe of microprocessor to be used for host communication. "00" = 8051 intel asynchronous "01" = 68k motorola asynchronous "10" = x86 intel synchronous "11" = 860 motorola synchronous n ote : this pin is internally pulled ?low? with a 50k ? resistor. ttip0 ttip1 ttip2 ttip3 ttip4 ttip5 ttip6 ttip7 e3 g4 f17 c16 r2 n2 n16 p16 o transmit differential tip output ttip is the positive differential output to the line interface. along with the tring signal, these pins should be coupled to a 1:2 step up transformer for proper opera - tion. tring0 tring1 tring2 tring3 tring4 tring5 tring6 tring7 e2 f3 f15 e16 p2 n4 r15 p17 o transmit differential ring output tring is the negative differential output to the line interface. along with the ttip signal, these pins should be coupled to a 1:2 step up transformer for proper opera - tion. tpos0 tpos1 tpos2 tpos3 tpos4 tpos5 tpos6 tpos7 c5 a4 b14 d14 v4 u5 v15 t14 i tpos/tdata input transmit digital input pin. in dual rail mo de, this pin is the transmit positive data input. in single rail mode, this pin is the transmit non-return to zero (nrz) data input. n ote : internally pulled "low" with a 50k ? resistor. tneg0 tneg1 tneg2 tneg3 tneg4 tneg5 tneg6 tneg7 c4 b5 d13 b15 u4 v5 u14 r14 i transmitter negative nrz data input in dual rail mode, this signal is the negative-rail input data for the transmitter. in single rail mode, this pin can be left unconnected while in host mode. however, in hardware mode, this pin is used to select the type of encoding/decoding for the e1/ t1 data format. connecting this pin ?low? enables hdb3 in e1 or b8zs in t1. connecting this pin ?high? selects ami data format. n ote : internally pulled ?low? with a 50k ? resistor.
xrt83sh38 9 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 tclk0 tclk1 tclk2 tclk3 tclk4 tclk5 tclk6 tclk7 b4 a3 a15 c14 t3 t5 v16 u15 i transmit clock input tclk is the input facility clock used to sample the incoming tpos/tneg data. if tclk is absent, pulled "low", or pulled "high", the transmitter outputs at ttip/ tring sends an all zero signal to the line. tpos/tneg data can be sampled on either edge of tclk selected by tclke. n ote : tclke is a global setting that applies to all 8 channels. taos0 taos1 taos2 taos3 taos4 taos5 taos6 taos7 d6 b6 a5 c6 t6 u6 v6 r6 i transmit all ones for channel hardware mode only setting this pin ?high? enables the transmission of an all ones pattern to the line from ttip/tring. if this pin is pulled ?low?, the transmitters operate in normal throughput mode. n ote : internally pulled ?low? with a 50k ? resistor for all channels. this feature is available in host mode by programm ing the appropriate channel register. txon0 txon1 txon2 txon3 txon4 txon5 txon6 txon7 a13 d12 c12 b12 v13 u13 r12 r13 i transmit on/off input upon power up, the transmitters are powered off. turning the transmitters on or off is selected through the microprocesso r interface by programming the appropri - ate channel register while in host mode. however, if txoncntl is set "high" in the appropriate global register or if in ha rdware mode, the activi ty of the transmitter outputs is controlled by the txon pins. n ote : txon is ideal for redundancy applications. see the redundancy applications section of this datasheet for more details. internally pulled "low" with a 50k ? resistor. s ignal n ame bga l ead # t ype d escription
xrt83sh38 10 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit microprocessor interface s ignal n ame bga l ead # t ype d escription hw/ host t10 i mode control input this pin is used to select host mode or hardware mode. by default, the liu is set in hardware mode. to use host mode, this pin must be pulled "low". n ote : internally pulled ?high? with a 50k ? resistor. wr _r/ w /eqc0 d7 i write input(r/ w )/equalizer control signal 0 host mode this pin is used to communicate a read or write operation according to the which microprocessor is chosen. see the micropr ocessor section of this datasheet for details. hardware mode eqc[4:0] are used to set the receiver gain, receiver impedance and the transmit line build out. see table 22 for more details. n ote : internally pulled ?low? with a 50k ? resistor. rd _ds/eqc1 c7 i read input (data strobe)/equalizer control signal 1 host mode this pin is used to communicate a read or write operation according to the which microprocessor is chosen. see the micropr ocessor section of this datasheet for details. hardware mode eqc[4:0] are used to set the receiver gain, receiver impedance and the transmit line build out. see table 22 for more details. n ote : internally pulled ?low? with a 50k ? resistor. ale/eqc2 a7 i address latch input (address strobe) host mode this pin is used to latch the address contents into the internal registers within the liu device. see the microprocessor section of this datasheet for details. hardware mode eqc[4:0] are used to set the receiver gain, receiver impedance and the transmit line build out. see table 22 for more details. n ote : internally pulled ?low? with a 50k ? resistor. cs /eqc3 b7 i chip select input - host mode: host mode this pin is used to initiate communicatio n with the microprocessor interface. see the microprocessor section of this datasheet for details. hardware mode eqc[4:0] are used to set the receiver gain, receiver impedance and the transmit line build out. see table 22 for more details. n ote : internally pulled ?low? with a 50k ? resistor.
xrt83sh38 11 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 rdy /eqc4 a6 i/o ready output (data transfer acknowledge) host mode (parallel microprocessor) if pin ser_ par is pulled "low", this output pin from the microprocessor block is used to inform the local p that the read or write operation has been completed and is waiting for the next command. see the mi croprocessor section of this datasheet for details. host mode (serial interface) if pin ser_ par is pulled "high", this output pin from the serial interface is used to read back the regsiter content s. see the microprocessor se ction of this datasheet for details. hardware mode eqc[4:0] are used to set the receiver gain, receiver impedance and the transmit line build out. see table 22 for more details. n ote : internally pulled ?low? with a 50k ? resistor. d[7]/loop14 d[6]/loop04 d[5]/loop15 d[4]/loop05 d[3]/loop16 d[2]/loop06 d[1]/loop17 d[0]/loop07 t7 u7 v7 v8 v9 u8 u9 r7 i/o bi-directional data bus/loopback mode select host mode these pins are used for the 8-bit bi-directional data bus to allow data transfer to and from the microprocessor interface. hardware mode (channels 4 through 7) these pins are used to select the loopback mode. each channel has two loopback pins loop[1:0]. "00" = no loopback "01" = analog local loopback "10" = remote loopback "11" = digital loopback n ote : internally pulled ?low? with a 50k ? resistor. a[7]/loop13 a[6]/loop03 a[5]/loop12 a[4]/loop02 a[3]/loop11 a[2]/loop01 a[1]/loop10 a[0]/loop00 a12 b11 c11 d11 a11 b10 a10 c10 i direct address bus/loopback mode select host mode these pins are used for the 8-bit direct address bus to allow access to the internal registers within the mi croprocessor interface. hardware mode (channels 0 through 3) these pins are used to select the loopback mode. each channel has two loopback pins loop[1:0]. "00" = no loopback "01" = analog local loopback "10" = remote loopback "11" = digital loopback n ote : internally pulled ?low? with a 50k ? resistor. s ignal n ame bga l ead # t ype d escription
xrt83sh38 12 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit jitter attenuator clock synthesizer pclk/ataos t13 i synchronous microprocessor clock/automatic transmit all ones host mode this synchronous input clock is used as the internal master clock to the microproces - sor interface when configured for in a synchronous mode. hardware mode this pin is used select an all ones signal to the line interface through ttip/tring any time that a loss of signal occurs. this fe ature is avaiable in host mode by program - ming the appropriate global register. n ote : internally pulled ?low? with a 50k ? resistor. int l16 o interrupt output/turns ratio select (external impedance mode) host mode this signal is asserted "low" when a change in alarm status occurs. once the status registers have been read, the interrupt pin will return "high". gie (global interrupt enable) must be set "high" in the appropriate global register to enable interrupt gen - eration. n otes : 1. this pin is an open-drain outpu t that requires an external 10k ? pull-up resistor. 2. internally pulled ?low? with a 50k ? resistor. s ignal n ame bga l ead # t ype d escription jasel0 jasel1 a14 b13 i jitter attenuator select pins hardware mode jasel[1:0] pins are used to plac e the jitter attenuator in t he transmit path, the receive path or to disable it. n ote : these pins are internally pulled ?low? with 50k ? resistors. s ignal n ame bga l ead # t ype d escription mclkout h1 o synthesized master clock output this signal is the output of the master clock synthesizer pll which is at t1 or e1 rate based upon the mode of operation. s ignal n ame bga l ead # t ype d escription disabled transmit receive receive ja path ja bw hz -------- 32/32 32/32 64/64 fifo size ----- 3 3 3 ----- 10 10 1.5 0 0 1 1 jasel1 0 1 0 1 jasel0 t1 e1
xrt83sh38 13 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 mclkt1 k1 i t1 master clock input this signal is an independent 1.544mhz clock for t1 systems with accuracy better than 50ppm and du ty cycle within 40% to 60%. mclk t1 is used in the t1 mode. n ote : all channels must operate at the same clock rate, either t1, e1 or j1. this pin is internally pulled "low" with a 50k ? resistor. mclke1 j1 i e1 master clock input a 2.048mhz clock for with an accuracy of better than 50ppm and a duty cycle of 40% to 60% can be provided at this pin. in systems that have only one master clock source available (e1 or t1), that cloc k should be connected to both mclke1 and mclkt1 inputs for proper operation. n ote : all channels of the xrt83sh38 must be operated at the same clock rate, either t1, e1 or j1. this pin is internally pulled ?low? with a 50k ? resistor. clksel0 clksel1 clksel2 a8 b8 c8 i clock select inputs for master clock synthesizer hardware mode only clksel[2:0] are input signals to a progra mmable frequency synt hesizer that can be used to generate a master clock from an external accurate clock source according to the table below. mclkrate is automati cally generated from the state of the eqc[4:0] pins. n ote : these pins are internally pulled ?low? with a 50k ? resistor. s ignal n ame bga l ead # t ype d escription 2048 2048 2048 1544 mclke1 khz 8 16 16 56 8 56 64 64 128 256 256 128 2048 2048 1544 1544 mclkt1 khz 1544 x x x 1544 x x x x x x x 2048 1544 2048 clkout/ khz 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 0 0 1 1 clksel0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0 clksel1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 clksel2 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 1544 2048 x x 2048 1544 0 1 0 1 mclkrate 1 0 1 0 0 1 0 1 1 0 1 0 0 1
xrt83sh38 14 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit alarm functions/redundancy support s ignal n ame bga l ead # t ype d escription gauge j18 i twisted pair cable wire gauge select hardware mode only this pin is used to match the frequency characteristics according to the gauge of wire used in telecom circuits. by default, the liu is matched to 22 gauge or 24 gauge wire. to select 26 gauge, this pin must be pulled "high". n ote : internally pulled ?low? with a 50k ? resistor. dmo0 dmo1 dmo2 dmo3 dmo4 dmo5 dmo6 dmo7 d5 d4 c15 c13 r5 p4 u17 v14 o digital monitor output when no transmit output pulse is detected for more than 128 tclk cycles within the transmit output buffer, the dmo pin will go "high" for a minimum of one tclk cycle. dmo will remain "high" until the transmitter sends a valid pulse. n ote : this pin can be used for redundancy applications to initiate an automatic switch to a backup card. reset t8 i hardware reset input active low signal. when this pin is pulled "low" for more than 10s, the internal reg - isters are set to their default state. s ee the register descripti on for the default val - ues. n ote : internally pulled "high" with a 50k ? resistor. sr/ dr k4 i single-rail/dual-rail data format hardware mode only this pin is used to control the data format on the facility side of the liu to interface to a framer or mapper/asic device. by defaul t, dual rail mode is selected which relies upon the framer to handle the encoding/decoding functions. to select single rail mode, this pin must be pulled "high". if single rail mode is selected, the liu can encode/decode ami or b8zs/hdb3 data formats. n ote : internally pulled ?low? with a 50k ? resistor. rxtsel u11 i receiver termination select hardware mode this pin is used to select between the internal and external impedance modes for the receive path. by default, the receiv ers are configured for external impedance mode, which is ideal for redundancy applications without relays. to select internal impedance, this pin must be pulled "high". host mode internal/external impedance can be selected by programming t he appropriate chan - nel registers. however, to assist in red undancy applications, this pin can be used for a hard switch if the rxtcntl bit is set "high" in the appropriate global register. if rxtcntl is set "high", the individual rxtsel register bits are ignored. n ote : this pin is internally pulled ?low? with a 50k ? resistor. txtsel v11 i transmitter termination select hardware mode this pin is used to select between the internal and external impedance modes for the transmit path. by default, the rece ivers are configured for external impedance mode, which is ideal for redundancy applications without relays. to select internal impedance, this pin must be pulled "high". n ote : this pin is internally pulled "low".
xrt83sh38 15 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 tersel1 tersel0 t11 r11 i termination impedance select hardware mode only these pins are used to select the transmit ter and receiver impedance. by default, the impedance is set to 100 ? . "00" = 100 ? "01" = 110 ? "10" = 75 ? "11" = 120 ? n ote : these pins are internally pulled "low" with a 50k ? resistor. test u12 i factory test mode for normal operation, the test pin should be tied to ground. n ote : internally pulled "low" with a 50k ? resistor. ict v12 i in circuit testing when this pin is tied "low", all output pins are forced to "high" impedance for in cir - cuit testing. n ote : internally pulled "high" with a 50k ? resistor. s ignal n ame bga l ead # t ype d escription
xrt83sh38 16 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit serial port and jtag s ignal n ame bga l ead # t ype d escription ser_ par p18 i serial/parallel select input (host mode only) this pin is used in the host mode to se lect between the parallel microprocessor or serial interface. by default, the host mode operates in the parallel micropro - cessor mode. to configure the device for a serial interface, this pin must be pulled "high". n ote : internally pulled ?low? with a 50k ? resistor. sclk t13 i serial clock input (host mode only) if pin ser_ par is pulled "high", this input pin is used the timing reference for the serial microprocessor interface. see the microprocessor section of this datasheet for details. sdi c10 i serial data input (host mode only) if pin ser_ par is pulled "high", this input pin from the serial interface is used to input the serial data for read and write operations. see the microprocessor section of this datasheet for details. sdo r7 o serial data output (host mode only) if pin ser_ par is pulled "high", this output pin from the serial interface is used to read back the regsiter contents. see the microprocesso r section of this datasheet for details. jtagtip jtagring e18 b18 analog jtag positive pin analog jtag negative pin tdo b1 test data out this pin is used as the output data pin for the boundary scan chain. tdi r1 test data in this pin is used as the input data pin for the boundary scan chain. tck n1 test clock input this pin is used as the input clock source for the boundary scan chain. tms e1 test mode select this pin is used as the input mode select for the boundary scan chain. nc a1 a18 n18 p18 v1 v18 **** no connect pins
xrt83sh38 17 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 power and ground s ignal n ame bga l ead # t ype d escription tgnd0 tgnd1 tgnd2 tgnd3 tgnd4 tgnd5 tgnd6 tgnd7 d3 f2 e15 c17 r3 p3 t16 r16 **** transmitter analog ground it?s recommended that all ground pins of this device be tied together. tvdd0 tvdd1 tvdd2 tvdd3 tvdd4 tvdd5 tvdd6 tvdd7 e4 f4 f16 e17 r4 p1 n15 p15 **** transmit analog power supply (3.3v 5%) tvdd can be shared with dvdd. however, it is recommended that tvdd be isolated from the analog power supply rvdd. for best results, use an internal power plane for isolation. if an internal power plane is not available, a ferrite bead can be used. each power supply pin should be bypassed to ground through an external 0.1 f capacitor. rvdd0 rvdd1 rvdd2 rvdd3 rvdd4 rvdd5 rvdd6 rvdd7 c2 e5 g16 d16 v2 n3 n17 u18 **** receive analog power supply (3.3v 5%) rvdd should not be shared with other power supplies. it is recommended that rvdd be isolated from the digital pow er supply dvdd and the analog power supply tvdd. for best results, use an in ternal power plane for isolation. if an internal power plane is not available, a ferrite bead can be used. each power supply pin should be bypassed to ground through an external 0.1 f capacitor. rgnd0 rgnd1 rgnd2 rgnd3 rgnd4 rgnd5 rgnd6 rgnd7 d2 g3 g17 d17 t2 m2 m17 r17 **** receiver analog ground it?s recommended that all ground pins of this device be tied together. avdd k17 j3 j2 **** analog power supply (3.3v 5%) avdd should be isolated from the digital power supplies. for best results, use an internal power plane for isolation. if an internal power plane is not available, a ferrite bead can be used. each power supply pin should be bypassed to ground through at least one 0.1 f capacitor. agnd j17 k3 l4 **** analog ground it?s recommended that all ground pins of this device be tied together.
xrt83sh38 18 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit dvdd r9 u10 k18 d9 d10 k15 a9 j4 **** digital power supply (3.3v 5%) dvdd should be isolated from the analog power supplies. for best results, use an internal power plane for isolation. if an internal power plane is not available, a ferrite bead can be used. every tw o dvdd power supply pins should be bypassed to ground through at least one 0.1 f capacitor. dgnd r8 t9 h17 b9 d8 c9 g15 k2 **** digital ground it?s recommended that all ground pins of this device be tied together. s ignal n ame bga l ead # t ype d escription
xrt83sh38 19 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 functional description the xrt83sh38 is a fully integrated 8-channel short-haul line interface unit (liu) that operates from a single 3.3v power supply. using internal termination, the liu prov ides one bill of materials to operate in t1, e1, or j1 mode with minimum external components. the liu features are programmed through a standard microprocessor interface or controlled thro ugh hardware mode. exar?s li u has patented high impedance circuits that allow the transmitter ou tputs and receiver inputs to be high impedance when experiencing a power failure or when the liu is powered off. key design fe atures within the liu optimize 1:1 or 1+1 redundancy and non-intrusive monitoring app lications to ensure reliability without usin g relays. the on-chip clock synthesizer generates t1/e1/j1 clock rates from a selectable external clock frequency and outputs a clock reference of the line rate chosen. additional features include rl os, a 16-bit lcv counter for each channel, ais, qrss generation/detection, network loop code generation/de tection, taos, dmo, and diagnostic loopback modes. 1.0 hardware mode vs host mode the liu supports a parallel or (serial) microprocessor interface (host mode) for programming the internal features, or a hardware mode that can be used to configure the device. 1.1 feature differences in hardware mode some features within the hardware mode are not suppor ted on a per channel basis. the differences between hardware mode and host mode are descibed below in table 1 . t able 1: d ifferences b etween h ardware m ode and h ost m ode f eature h ost m ode h ardware m ode tx test patterns fully supported qrss diagnostic patterns are not available in hardware mode. the taos feature is available. rxres[1:0] per channel in hardware mode, rxres[1:0] is a global setting that applies to all channels. tersel[1:0] per channel in hardware mode, tersel[1:0] is a global setting that applies to all channels. eqc[4:0] per channel in hardware mode, the eqc[4:0] is a global setting that applies to all channels. n ote : in host mode, all channels have to operate at one line rate t1 or e1, however each channel can have an individual line build out. dual loopback fully supported in hardware mode, dual loopback mode is not supported. remote, analog local, and digital loopback modes are available. jasel[1:0] per channel in hardware mode, the jitter attenuat or selection is a global setting that applies to all channels. rxtsel per channel in hardware mode, the receive termination select is a global set - ting that applies to all channels. txtsel per channel in hardware mode, the transmit termination select is a global set - ting that applies to all channels.
xrt83sh38 20 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit 2.0 master clock generator using a variety of external clock sources, the on-chi p frequency synthesizer generat es the t1 (1.544mhz) or e1 (2.048mhz) master clo cks necessary for the transmit pulse shap ing and receive clock recovery circuit. there are two master clock inputs mclke1 and mclkt1. in systems where both t1 and e1 master clocks are available these clocks can be connected to the respective pins. all channels of a given xrt83sh38 must be operated at the same clock rate, either t1, e1 or j1 modes. in systems that have only one master clock source available (e1 or t1), that clock should be connected to both mclke1 and mclkt1 inputs for proper operation. t1 or e1 master clocks can be generat ed from 8khz, 16khz, 56khz, 64khz, 128khz and 256khz external clocks under the control of clksel[2:0] inputs according to eqc[4:0] determine the t1/e1 operating mode. see for details. f igure 3. t wo i nput c lock s ource f igure 4. o ne i nput c lock s ource t able 2: m aster c lock g enerator mclke1 k h z mclkt1 k h z clksel2 clksel1 clksel0 mclkrate m aster c lock k h z 2048 2048 0 0 0 0 2048 2048 2048 0 0 0 1 1544 2048 1544 0 0 0 0 2048 1544 1544 0 0 1 1 1544 1544 1544 0 0 1 0 2048 2048 1544 0 0 1 1 1544 8 x 0 1 0 0 2048 8 x 0 1 0 1 1544 mclke1 mclkt1 mclkout 1.544mhz or 2.048mhz 2.048mhz +/-50ppm 1.544mhz +/-50ppm two input clock sources mclke1 mclkt1 mclkout 1.544mhz or 2.048mhz one input clock source input clock options 8khz 16khz 56khz 64khz 128khz 256khz 1.544mhz 2.048mhz
xrt83sh38 21 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 3.0 receive path line interface the receive path of the xrt83sh38 liu consists of 8 in dependent t1/e1/j1 receivers. the following section describes the complete receive path from rtip/rring inputs to rclk /rpos/rneg outputs. a simplified block diagram of the receive path is shown in figure 5 . f igure 5. s implified b lock d iagram of the r eceive p ath 3.1 line termination (rtip/rring) 3.1.1 case 1: internal termination the input stage of the receive path accepts standard t1/e 1/j1 twisted pair or e1 coaxial cable inputs through rtip and rring. the physical interface is optimized by placing the terminating im pedance inside the liu. this allows one bill of materials for all modes of operat ion reducing the number of external components necessary in system design. the receive termination impedance is selected by programming tersel[1:0] to match the line impedance. selecting the internal impedance is shown in table 3 . 16 x 0 1 1 0 2048 16 x 0 1 1 1 1544 56 x 1 0 0 0 2048 56 x 1 0 0 1 1544 64 x 1 0 1 0 2048 64 x 1 0 1 1 1544 128 x 1 1 0 0 2048 128 x 1 1 0 1 1544 256 x 1 1 1 0 2048 256 x 1 1 1 1 1544 t able 3: s electing the i nternal i mpedance tersel[1:0] r eceive t ermination 0h (00) 100 ? 1h (01) 110 ? 2h (10) 75 ? 3h (11) 120 ? t able 2: m aster c lock g enerator mclke1 k h z mclkt1 k h z clksel2 clksel1 clksel0 mclkrate m aster c lock k h z hdb3/b8zs decoder rx jitter attenuator clock & data recovery peak detector & slicer rtip rring rclk rneg rpos
xrt83sh38 22 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit the xrt83sh38 has the abilit y to switch the internal termination to "high" impedance by programming rxtsel in the appropriate channel register. for internal termination, set rxtsel to "1". by default, rxtsel is set to "0" ("high" impedance). for redundancy ap plications, a dedicated hardware pin (rxtsel) is also available to control the receive termination for all chan nels simultaneously. this hardware pin takes priority over the register setting if rxtcntl is se t to "1" in the appropriate global register. if rxtcntl is set to "0", the state of this pin is ignored. see figure 6 for a typical connection diagram using the internal termination. f igure 6. t ypical c onnection d iagram u sing i nternal t ermination 3.1.2 case 2: internal termination with on e external fixed resistor for all modes along with the internal termination, a high precision exte rnal fixed resistor can be used to optimize the return loss. this external resistor can be used for all modes of operation ensu ring one bill of mate rials. there are three resistor values that can be used by setting th e rxres[1:0] bits in the appropriate channel register. selecting the value for the external fixed resistor is shown in table 4 . by default, rxres[1:0] is set to "none" for no external fi xed resistor. if an external fixed resistor is used, the xrt83sh38 uses the parallel combination of the external fixed resistor and the internal termination as the input impedance. see figure 7 for a typical connection diagram using the external fixed resistor. n ote : without the external resistor, the xrt83sh38 meets all retu rn loss specifications. this mode was created to add flexibility for optimizing return loss by using a high precision external resistor. f igure 7. t ypical c onnection d iagram u sing o ne e xternal f ixed r esistor 3.2 clock and data recovery the receive clock (rclk) is recovered by the clock and data recovery circuitry. an internal pll locks on the incoming data stream and outputs a clock that?s in p hase with the incoming signal . this allows for multi- channel t1/e1/j1 signals to arrive from different timing sources and remain independent. in the absence of an incoming signal, rclk maintains its timing by using the internal master clock as its reference. the recovered t able 4: s electing the v alue of the e xternal f ixed r esistor r x res[1:0] e xternal f ixed r esistor 0h (00) none 1h (01) 240 ? 2h (10) 210 ? 3h (11) 150 ? r tip r ring xrt83sh38 liu 1:1 internal impedance line interface t1/e1/j1 one bill of materials receiver input r tip r ring xrt83sh38 liu 1:1 internal impedance line interface t1/e1/j1 r r=240 ? , 210 ? , or 150 ? receiver input
xrt83sh38 23 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 data can be updated on either edge of rclk. by default , data is updated on the rising edge of rclk. to update data on the falling edge of rclk, set rclke to "1" in the appropriate global register. figure 8 is a timing diagram of the receive data updated on the rising edge of rclk. figure 9 is a timing diagram of the receive data updated on the fallin g edge of rclk. the timing specifications are shown in table 5 . f igure 8. r eceive d ata u pdated on the r ising e dge of rclk f igure 9. r eceive d ata u pdated on the f alling e dge of rclk n ote : vdd=3.3v 5%, t a =25c, unless otherwise specified 3.2.1 receive sensitivity to meet short haul requirements, the xrt83sh38 can a ccept t1/e1/j1 signals that have been attenuated by 12db of flat loss in e1 mode or by 655 feet of cable loss along with 6db of flat loss in t1 mode. however, the xrt83sh38 can tolerate cable loss and flat loss beyond the industry specifications. the receive sensitivity in the short haul mode is approximately 4,000 feet without experiencing bit errors, lof, pattern synchronization, etc. although data integr ity is maintained, the rlos function (i f enabled) will report an rlos condition t able 5: t iming s pecifications for rclk/rpos/rneg p arameter s ymbol m in t yp m ax u nits rclk duty cycle r cdu 45 50 55 % receive data setup time r su 150 - - ns receive data hold time r ho 150 - - ns rclk to data delay r dy - - 40 ns rclk rise time (10% to 90%) with 25pf loading rclk r - - 40 ns rclk fall time (90% to 10%) with 25pf loading rclk f - - 40 ns rclk rpos or rneg r dy rclk r rclk f r oh rclk rpos or rneg r dy rclk f rclk r r oh
xrt83sh38 24 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit according to the receiver loss of sign al section in this datasheet. the test configuration for measuring the receive sensitivity is shown in figure 10 . f igure 10. t est c onfiguration for m easuring r eceive s ensitivity 3.2.2 interference margin the interference margin for the xrt83sh38 will be added when the fi rst revision of silicon arrives. the test configuration for measuring the interference margin is shown in figure 11 . f igure 11. t est c onfiguration for m easuring i nterference m argin 3.2.3 general alarm detection and interrupt generation the receive path detects rlos, ais, qrpd and fls. th ese alarms can be individually masked to prevent the alarm from triggering an interrupt. to enable interrupt generation, the global interrupt enable (gie) bit must be set "high" in the appropriate global register. any time a change in status occurs (it the alarms are enabled), the interrupt pin will pull "low" to indicate an alarm has occurred. once the status register s have been read, the int pin will return "high". the status registers are reset upon read (rur). the inte rrupts are categorized in a hierarchical process block. figure is a simplified block diagram of the interrupt generation process. n ote : the interrupt pin is an open-drain output that requires a 10k ? external pull-up resistor. 3.2.3.1 rlos (recei ver loss of signal) in t1 mode, rlos is declared if an incoming signal has no transitions over a per iod of 175 +/-75 contiguous pulse intervals. however, the xrt83sh38 liu has a bu ilt in analog rlos so that the user can be notified when the amplitude of the incoming signal has been atte nuated -9db below the equalizer gain setting. for example: in t1 or e1 short haul mode, the equalizer gain setting is 15db. once the input reaches an amplitude of -24db below nominal, the liu will declare rlos. the rlos circuitry clears when the input reaches +3db relative to where it was declared. this +3db value is a pre-determined hysteresis so that transients will not cause the rlos to clear. in e1 mode, rlos is declared if an incoming signal has no transitions for n consecutiv e pulse intervals, where 10 n 255. according to g.775, no transitions in e1 mode is defined between -9db and -35db below nominal. figure 12 is a simplified block diagram of the analog rlos function. table 6 summarizes the analog rlos values for the different equalizer gain settings. network analyzer e1 = prbs 2 15 - 1 t1 = prbs 2 23 - 1 external loopback xrt83sh38 14-channel long haul liu cable loss flat loss tx tx rx rx w&g ant20 sinewave generator flat loss w&g ant20 network analyzer cable loss xrt83sh38 14-channel liu e1 = 1,024khz t1 = 772khz e1 = prbs 2 15 - 1 t1 = prbs 2 23 - 1 tx tx rx rx external loopback
xrt83sh38 25 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 f igure 12. a nalog r eceive l os of s ignal for t1/e1/j1 n ote : for programming the equalizer gain setting on a per channel basis, see the micr oprocessor register map for details. 3.2.3.2 exlos (extended loss of signal) by enabling the extended loss of signal by programming the appropriate channel register, the digital rlos is extended to count 4,096 consecutive zeros before declar ing rlos in t1 and e1 mode. by default, exlos is disabled and rlos operates in normal mode. 3.2.3.3 ais (alarm indication signal) the xrt83sh38 adheres to the itu-t g.775 specification fo r an all ones pattern. the alarm indication signal is set to "1" if an all ones pattern (at least 99.9% ones d ensity) is present for t, where t is 3ms to 75ms in t1 mode. ais will clear when the ones dens ity is not met within the same time period t. in e1 mode, the ais is set to "1" if the incoming signal has 2 or less zeros in a 512-bit window. ais will clear when th e incoming signal has 3 or more zeros in the 512-bit window. 3.2.3.4 flsd (fifo limi t status detection) the purpose of the fifo limit status is to indicate when the read and write fifo pointers are within a pre- determined range (over-flow or under-flow indication). the flsd is set to "1" if the fifo read and write pointers are within 3-bits. 3.2.3.5 lcvd (line code violation detection) the liu contains 8 independent, 16-bit lcv counters. when the counters reach full-scale, they remain saturated at ffffh until they are reset globally or on a per channel basis. for performance monitoring, the counters can be updated globally or on a per channel ba sis to place the contents of the counters into holding registers. the liu uses an indirect address bus to acce ss a counter for a given channel. once the contents of the counters have been placed in holding registers, they can be individually read out 8-bits at a time according to the bytesel bit in the appropriate global register. by default, the lsb is placed in the holding register until the bytesel is pulled "high" where up on the msb will be placed in the hold ing register for read back. once both bytes have been read, the next channel may be selected for read back. by default, the lvc/ofd will be set to a "1" if the receiver is currently detecting line code violations or excessive zeros for hdb3 (e1 mode) or b8zs (t1 mode). in ami mode, t he lcvd will be set to a "1" if the receiver is currently detecting bipola r violations or excessive zeros. however, if the liu is configured to t able 6: a nalog rlos d eclare /c lear (t ypical v alues ) for t1/e1 g ain s etting d eclare c lear 15db (short haul mode) -24db -21db 29db (monitoring gain mode) -38db -35db normalized up to eqc[4:0] setting declare los clear los -9db +3db clear los declare los +3db -9db normalized up to eqc[4:0] setting
xrt83sh38 26 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit monitor the 16-bit lcv counter by programming the appr opriate global register, the lcv/ofd will be set to a "1" if the counter saturates. 3.3 receive jitter attenuator the receive path has a dedicated jitter attenuator that reduces phase and frequency jitter in the recovered clock. the jitter attenuator uses a data fifo (first in first out) with a programmable depth of 32-bit or 64-bit. if the liu is used for line synchron ization (loop timing systems), the ja should be enabled. when the read and write pointers of the fifo are within 2-bits of ov er-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corrup tion. when this condition occurs, the jitter attenuator will not attenuate input jitter until the read/write pointer?s position is outside the 2- bit window. in t1 mode, the bandwidth of the ja is always set to 3hz. in e1 mode, the bandwidth is programmable to either 10hz or 1.5hz (1.5hz automati cally selects the 64-bit fifo depth). the ja has a clock delay equal to ? of the fifo bit depth. n ote : if the liu is used in a multiplexer/mapper application where stuffing bits are typically re moved, the transmit path has a dedicated jitter attenuator to smooth out the gapped clock. see the transmit section of this datasheet. 3.4 hdb3/b8zs decoder in single rail mode, rpos can decode ami or hdb3/b8zs signals. for e1 mode, hdb3 is defined as any block of 4 successive zeros replaced with ooov or boov, so that two successive v pulses are of opposite polarity to prevent a dc component. in t1 mode, 8 successive zeros are replaced with ooovbovb. if the hdb3/b8zs decoder is selected, the re ceive path removes the v and b pulses so that the original data is output to rpos. 3.5 rpos/rneg/rclk the digital output data can be programmed to either single rail or dual rail formats. figure 13 is a timing diagram of a repeating "0011" pattern in single-rail mode. figure 14 is a timing diagram of the same fixed pattern in dual rail mode. f igure 13. s ingle r ail m ode w ith a f ixed r epeating "0011" p attern f igure 14. d ual r ail m ode w ith a f ixed r epeating "0011" p attern rclk rpos 00 0 1 1 rclk rpos 00 0 1 1 rneg
xrt83sh38 27 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 3.6 rxmute (receiver los with data muting) the receive muting function can be selected by setting rx mute to "1" in the appropriate global register. if selected, any channel that experien ces an rlos condition will automatic ally pull rpos and rneg "low" to prevent data chattering. if rlos does not occur, the rxmute will remain inactive until an rlos on a given channel occurs. the default setting for rxmute is "0" which is disabled . a simplified block diagram of the rxmute function is shown in figure 15 . f igure 15. s implified b lock d iagram of the r x mute f unction rlos rxmute rpos rneg
xrt83sh38 28 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit 4.0 transmit path line interface the transmit path of the xrt83sh38 liu consists of 8 independent t1/e1/j1 transmitters. the following section describes the complete trans mit path from tclk/tpos/tneg in puts to ttip/tring outputs. a simplified block diagram of the transmit path is shown in figure 16 . f igure 16. s implified b lock d iagram of the t ransmit p ath 4.1 tclk/tpos/tneg digital inputs in dual rail mode, tpos and tneg are the digital inputs for the transmit path. in single rail mode, tneg has no function and can be left unconnected. the xrt83sh3 8 can be programmed to sample the inputs on either edge of tclk. by default, data is sa mpled on the falling edge of tclk. to sample data on the rising edge of tclk, set tclke to "1" in the appropriate global register. figure 17 is a timing diagram of the transmit input data sampled on the falling edge of tclk. figure 18 is a timing diagram of the transmit input data sampled on the rising edge of tclk. the timing specifications are shown in table 7 . f igure 17. t ransmit d ata s ampled on f alling e dge of tclk f igure 18. t ransmit d ata s ampled on r ising e dge of tclk hdb3/b8zs encoder tx jitter attenuator timing control tx pulse shaper & pattern gen line driver ttip tring tclk tneg tpos tclk tpos or tneg tclk r tclk f t ho t su tclk tpos or tneg tclk f tclk r t ho t su
xrt83sh38 29 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 n ote : vdd=3.3v 5%, t a =25c, unless otherwise specified 4.2 hdb3/b8zs encoder in single rail mode, the liu can encode the tpos input signal to ami or hdb3/b8zs data. in e1 mode and hdb3 encoding selected, any sequence with four or more consecutive ze ros in the input w ill be replaced with 000v or b00v, where "b" indicates a pulse conforming to the bipolar rule and "v" representing a pulse violating the rule. an example of hdb3 encoding is shown in table 8 . in t1 mode and b8zs encoding selected, an input data sequence with eight or mo re consecutive zeros will be replaced using the b8zs encoding rule. an example with bipolar with 8 zero substitution is shown in table 9 . t able 7: t iming s pecifications for tclk/tpos/tneg p arameter s ymbol m in t yp m ax u nits tclk duty cycle t cdu 30 50 70 % transmit data setup time t su 50 - - ns transmit data hold time t ho 30 - - ns tclk rise time (10% to 90%) tclk r - - 40 ns tclk fall time (90% to 10%) tclk f - - 40 ns t able 8: e xamples of hdb3 e ncoding n umber of p ulses b efore n ext 4 z eros input 0000 hdb3 (case 1) odd 000v hdb3 (case 2) even b00v t able 9: e xamples of b8zs e ncoding c ase 1 p receding p ulse n ext 8 b its input + 00000000 b8zs 000vb0vb ami output + 000+-0-+ case 2 input - 00000000 b8zs 000vb0vb ami output - 000-+0+-
xrt83sh38 30 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit 4.3 transmit jitter attenuator the xrt83sh38 liu is ideal for multip lexer or mapper applications where the network data crosses multiple timing domains. as the higher data rates are de-multiple xed down to t1 or e1 data, stuffing bits are typically removed which can leave gaps in the incoming data stream. the transmit path has a dedicated jitter attenuator with a 32-bit or 64-bit fifo that is used to smooth the gapped clock into a steady t1 or e1 output. the maximum gap width of the 8-channel liu is shown in table 10 . n ote : if the liu is used in a lo op timing system, the receive pa th has a dedicated jitter attenuator. see the receive section of this datasheet. 4.4 taos (transmit all ones) the xrt83sh38 has the ability to transmit all ones on a per channel basis by pr ogramming the appropriate channel register. this function takes priority over th e digital data present on the tpos/tneg inputs. for example: if a fixed "0011" pattern is present on tpos in single rail mode and taos is enabled, the transmitter will output all ones. in addition, if di gital or dual loopback is selected, the data on the rpos output will be equal to the data on the tpos input. figure 19 is a diagram showing the all ones signal at ttip and tring. f igure 19. taos (t ransmit a ll o nes ) 4.5 transmit diagnostic features in addition to taos, the xrt83sh38 of fers diagnostic features for analyzing network integrity such as ataos and qrss on a per channel basis by programming the appr opriate registers. these diagnostic features take priority over the digital data present on tpos/tneg inpu ts. the transmitters will send the diagnostic code to the line and will be maintained in the digital loopback if selected. when the liu is responsible for sending diagnostic patterns, the liu is automati cally placed in the single rail mode. t able 10: m aximum g ap w idth for m ultiplexer /m apper a pplications fifo d epth m aximum g ap w idth 32-bit 20 ui 64-bit 50 ui taos 111
xrt83sh38 31 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 4.5.1 ataos (automatic transmit all ones) if ataos is selected by programming the appropriate global register, an ami all ones signal will be transmitted for each channel that experiences an rlos condition. if rlos does not occur, the ataos will remain inactive until an rlos on a given channel occurs. a simplifie d block diagram of the atao s function is shown in figure 20 . f igure 20. s implified b lock d iagram of the ataos f unction 4.5.2 qrss generation the xrt83sh38 can transmit a qrss random sequence to a remote location from ttip/tring. the polynomial is shown in table 11 . 4.5.3 t1 short haul line build out (lbo) the short haul transmitter output pulses are generated usin g a 7-bit internal dac (6-bit plus the msb sign bit). the line build out can be set to interface to five di fferent ranges of cable attenuation by programming the appropriate channel register. the pulse shape is divided into eight discrete time segments which are set to fixed values to comply with the pulse template. to program the eight segments individually to optimize a special line build out, see the arbitrary pulse section of this datasheet. the short haul lbo settings are shown in table 12 . t able 11: r andom b it s equence p olynomials r andom p attern t1 e1 qrss 2 20 - 1 2 15 - 1 t able 12: s hort h aul l ine b uild o ut lbo setting eqc[4:0] r ange of c able a ttenuation 08h (01000) 0 - 133 feet 09h (01001) 133 - 266 feet 0ah (01010) 266 - 399 feet 0bh (01011) 399 - 533 feet 0ch (01100) 533 - 655 feet rlos ataos taos ttip tring tx
xrt83sh38 32 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit 4.5.4 arbitrary pulse ge nerator for t1 and e1 the arbitrary pulse generator divides the pulse into eight individual segments. each segment is set by a 7-bit binary word by programming the appropriate channel regi ster. this allows the system designer to set the overshoot, amplitude, and undershoot for a unique line build ou t. the msb (bit 7) is a sign-bit. if the sign-bit is set to "0", the segment will move in a positive direction relative to a flat lin e (zero) condition. if this sign-bit is set to "1", the segment will move in a n egative direction relative to a flat lin e condition. the resolution of the dac is typically 60mv per lsb. th us, writing 7-bit = 1111111 will clamp the output at either voltage rail corresponding to a maximum amplitude. a pulse with numbered segments is shown in figure 21 . f igure 21. a rbitrary p ulse s egment a ssignment n ote : by default, the arbitrary segments are programmed to 0x00h. the transmitter outputs will result in an all zero pattern to the line interface. 4.6 dmo (digital monitor output) the driver monitor circuit is used to detect transmit dr iver failures by monitoring t he activities at ttip/tring outputs. driver failure may be caused by a short circui t in the primary transformer or system problems at the transmit inputs. if the transmitter of a channel has no output for more than 128 clock cycles, dmo goes "high" until a valid transmit pulse is detected . if the dmo interrupt is enabled, t he change in status of dmo will cause the interrupt pin to go "low". once th e status register is read , the interrupt pin will retu rn "high" and the status register will be reset (rur). 1 2 3 4 5 6 7 8 segment register 1 0xn8 2 0xn9 3 0xna 4 0xnb 5 0xnc 6 0xnd 7 0xne 8 0xnf
xrt83sh38 33 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 4.7 line termination (ttip/tring) the output stage of the transmit path generates standard return-to-zero (rz) signals to the line interface for t1/ e1/j1 twisted pair or e1 coaxial cable. the physica l interface is optimized by placing the terminating impedance inside the liu. this allows one bill of materials for all modes of operation re ducing the number of external components necessary in system design. the transmitter outputs only require one dc blocking capacitor of 0.68 f. for redundancy applications (or simply to tri- state the transmitters), set txtsel to a "1" in the appropriate channel register. a ty pical transmit interface is shown in figure 22 . f igure 22. t ypical c onnection d iagram u sing i nternal t ermination t tip t ring xrt83sh38 liu 1:2 internal impedance line interface t1/e1/j1 c=0.68uf one bill of materials transmitter output
xrt83sh38 34 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit 5.0 t1/e1 applications this applications section describes common t1/e1 system considerations along with references to application notes available for reference where applicable. 5.1 loopback diagnostics the xrt83sh38 supports several loopback modes for diag nostic testing. the following section describes the local analog loopback, remote loopback, digital loopback, and dual loopback modes. 5.1.1 local analog loopback with local analog loopback activated, the transmit outpu t data at ttip/tring is intern ally looped back to the analog inputs at rtip/rring. external inputs at rtip/rring are ignored while valid transmit output data continues to be sent to the line. a simplified block diagram of local analog loopback is shown in figure 23 . f igure 23. s implified b lock d iagram of l ocal a nalog l oopback n ote : the transmit diagnostic features such as taos and qrss ta ke priority over the transm it input data at tclk/tpos/ tneg. 5.1.2 remote loopback with remote loopback activated, the receive input data at rtip/rring is internally lo oped back to the transmit output data at ttip/tring. the remote loopback incl udes the receive ja (if enabled). the transmit input data at tclk/tpos/tneg are ignored while valid receive output data continues to be sent to the system. a simplified block diagram of remote loopback is shown in figure 24 . f igure 24. s implified b lock d iagram of r emote l oopback encoder decoder timing control data and clock recovery ja ja tx taos qrss ttip tring rtip rring tclk tpos tneg rclk rpos rneg rx encoder decoder timing control data and clock recovery ja ja tx rx taos qrss ttip tring rtip rring tclk tpos tneg rclk rpos rneg
xrt83sh38 35 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 5.1.3 digital loopback with digital loopback activated, the transmit input da ta at tclk/tpos/tneg is looped back to the receive output data at rclk/rpos/rneg. the digital loopback mode includes the transmit ja (if enabled). the receive input data at rtip/rri ng is ignored while va lid transmit output data continues to be sent to the line. a simplified block diagram of digital loopback is shown in figure 25 . f igure 25. s implified b lock d iagram of d igital l oopback 5.1.4 dual loopback with dual loopback activated, the remote loopback is combined with the digital lo opback. a simplified block diagram of dual loopback is shown in figure 26 . f igure 26. s implified b lock d iagram of d ual l oopback encoder decoder timing control data and clock recovery ja ja tx rx taos qrss ttip tring rtip rring tclk tpos tneg rclk rpos rneg encoder decoder timing control data and clock recovery ja ja tx rx taos qrss ttip tring rtip rring tclk tpos tneg rclk rpos rneg
xrt83sh38 36 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit 5.2 line card redundancy telecommunication system design requires signal integrity and reliability. when a t1/e1 prim ary line card has a failure, it must be swapped with a backup line card while maintaining connectivi ty to a backplane without losing data. system designers can achieve this by implementing common redundancy schemes with the xrt83sh38 liu. exar offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. rlos and dmo if an rlos or dmo condition occurs, the xrt83sh38 reports the alarm to the individual status registers on a per channel basis. however, for redundancy applicatio ns, an rlos or dmo alarm can be used to initiate an automatic switch to the back up card. for this application, two global pins rlos and dmo are used to indicate that one of the 8-channels has an rlos or dmo condition. typical redundancy schemes ? 1:1 one backup card for every primary card (facility protection) ? 1+1 one backup card for every primary card (line protection) ? n+1 one backup card for n primary cards 5.2.1 1:1 and 1+1 redundancy without relays the 1:1 facility protection and 1+1 lin e protection have one backup card fo r every primary card. when using 1:1 or 1+1 redundancy, the backup card has its transmitters tri-stated and its receivers in high impedance. this eliminates the need for external relays and provides one bill of materials for all interface m odes of operation. for 1+1 line protection, the receiver in puts on the backup card have the ab ility to monitor the line for bit errors while in high impedance. the transmit and receive se ctions of the liu device are described separately. 5.2.2 transmit interface with 1:1 and 1+1 redundancy the transmitters on the backup card should be tri-stated. select the appropriate impedance for the desired mode of operation, t1/e1/j1. a 0.68uf capacitor is used in series with ttip for blocking dc bias. see figure 27 . for a simplified block diagram of the transmit section for a 1:1 and 1+1 redundancy. f igure 27. s implified b lock d iagram of the t ransmit i nterface for 1:1 and 1+1 r edundancy t1/e1 line backplane interface primary card backup card xrt83sh38 tx tx 0.68uf 0.68uf internal impedence 1:2 1:2 xrt83sh38 internal impedence
xrt83sh38 37 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 5.2.3 receive interface with 1:1 and 1+1 redundancy the receivers on the backup card should be programmed for "high" impedance. since there is no external resistor in the circuit, the receiver s on the backup card will not load down the line interface. this key design feature eliminat es the need for relays a nd provides one bill of materials fo r all interface mo des of operation. select the impedance for the desired mode of operation, t1/e1/j1. to swap the primary card, set the backup card to internal impedance, then the primary card to "high" impedance. see figure 28 . for a simplified block diagram of the receive section for a 1:1 redundancy scheme. f igure 28. s implified b lock d iagram of the r eceive i nterface for 1:1 and 1+1 r edundancy "high" impedence internal impedence backplane interface primary card backup card xrt83sh38 rx t1/e1 line rx 1:1 1:1 xrt83sh38
xrt83sh38 38 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit 5.2.4 n+1 redundancy using external relays n+1 redundancy has one backup card for n primary cards. due to impedance mismatch and signal contention, external relays are necessary when using th is redundancy scheme. the relays create complete isolation between the primary cards and the backup card. this allows all transmit ters and receivers on the primary cards to be configured in in ternal impedance, providing one bill of material s for all interf ace modes of operation. the transmit and receive sections of the liu device are described separately. 5.2.5 transmit interface with n+1 redundancy for n+1 redundancy, the transmitters on all cards should be programmed for internal impedance. the transmitters on the backup card do not have to be tri-stated. to swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. a 0.68uf capacitor is used in series with ttip for blocking dc bias. see figure 29 for a simplified block diagram of the transmit section for an n+1 redundancy scheme. f igure 29. s implified b lock d iagram of the t ransmit i nterface for n+1 r edundancy backplane interface primary card xrt83sh38 tx line interface card 0.68uf t1/e1 line 0.68uf primary card tx 0.68uf primary card tx 0.68uf backup card tx t1/e1 line t1/e1 line internal impedence 1:2 1:2 1:2 xrt83sh38 xrt83sh38 xrt83sh38 internal impedence internal impedence internal impedence
xrt83sh38 39 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 5.2.6 receive interface with n+1 redundancy for n+1 redundancy, the receivers on the primary cards should be programmed for internal impedance. the receivers on the backup card should be programmed for "high" impedance mode. to swap the primary card, set the backup card to internal impedance, then the primary card to "high" impedance. see figure 30 for a simplified block diagram of the receive section for a n+1 redundancy scheme. f igure 30. s implified b lock d iagram of the r eceive i nterface for n+1 r edundancy backplane interface primary card xrt83sh38 rx line interface card primary card rx primary card rx backup card rx internal impedence t1/e1 line t1/e1 line t1/e1 line 1:1 1:1 1:1 xrt83sh38 xrt83sh38 xrt83sh38 internal impedence internal impedence "high" impedence
xrt83sh38 40 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit 5.3 power failure protection for 1:1 or 1+1 line card redundancy in t1/e1 applicatio ns, power failure could cause a line card to change the characteristics of the line impedance, causing a degrada tion in system performance. the xrt83sh38 was designed to ensure reliability during power failures. the liu has patented high imp edance circuits that allow the receiver inputs and the transmitter outputs to be in "high" impedance when the liu experiences a power failure or when the liu is powered off. n ote : for power failure protection, a transformer must be used to c ouple to the line interface. see the tan-56 application note for more details. 5.4 overvoltage and overcurrent protection physical layer devices such as lius that interface to telecommunications lines are exposed to overvoltage transients posed by environmental threats. an overvolt age transient is a pulse of energy concentrated over a small period of time, usually under a few milliseconds. these pulses are random and exceed the operating conditions of cmos transceiver ics. electronic equi pment connecting to data lines are susceptible to many forms of overvoltage transients such as lightning, ac power faults and electrostati c discharge (esd). there are three important standards when designing a te lecommunications system to withstand overvoltage transients. ? ul1950 and fcc part 68 ? telcordia (bellcore) gr-1089 ? itu-t k.20, k.21 and k.41 5.5 non-intrusive monitoring in non-intrusive monitoring applications, the transmitters are shut off by setting txon "low". the receivers must be actively receiving data without interfering with the line impedance. the xrt83sh38?s internal termination ensures that the line termi nation meets t1/e1 specifications for 75 ?, 100 ? or 120 ? while monitoring the data stream. system integrity is maintained by placing the non-intrusive receiver in "high" impedance, equivalent to that of a 1+1 redundancy app lication. a simplified blo ck diagram of non-intrusive monitoring is shown in figure 31 . f igure 31. s implified b lock d iagram of a n on -i ntrusive m onitoring a pplication line card transceiver non-intrusive receiver node xrt83sh38 xrt83sh38 data traffic
xrt83sh38 41 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 6.0 microprocessor interface the microprocessor interface can be a ccessed through a standard serial interface (bga package only) or a standard parallel microprocessor interface. the ser_ par pin is used to select betw een the two. by default, the chip is configured in the parallel microprocessor interace. for serial communication, this pin must be pulled ?high?. 6.1 serial microprocessor interface block the serial microprocessor uses a standard 3-pin serial port with cs , sclk, and sdi for programming the liu. optional pins such as sdo, int , and reset allow the ability to read back cont ents of the regi sters, monitor the liu via an interrupt pin, and reset the liu to its default co nfiguration by pulling rese t "low" for more than 10 s. a simplified block diagram of the serial microprocessor is shown in figure 32 . 6.1.1 serial timing information the serial port requires 24 bits of data applied to the sdi (serial data input) pin. the serial microprocessor samples sdi on the rising edge of sclk (serial clock input). the data is not latched into the device until all 24 bits of serial data have been sampled. a timing diagram of the serial microprocessor is shown in figure 33 . n ote : for applications without a free running sclk, a minimum of 1 sclk pulse must be applied when cs is ?high?, befrore pulling cs ?low?. f igure 32. s implified b lock d iagram of the s erial m icroprocessor i nterface f igure 33. t iming d iagram for the s erial m icroprocessor i nterface serial microprocessor interface cs sdi sclk sdo reset int hw/host ser_par r/w addr[0] - addr[7] don't care data[0] - data[7] cs sdi sclk 8-bit address 8-bit data 7-bit don't care 1=read 0=write sdo data[0] - data[7] readback
xrt83sh38 42 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit 6.1.2 24-bit serial data input descritption the serial data input is sampled on the rising edge of sclk. in readback mode, the serial data output is updated on the falling edge of sclk. the serial data must be applied to the liu lsb fi rst. the 24 bits of serial data are described below. 6.1.3 addr[7:0] (sclk1 - sclk8) the first 8 sclk cycles are used to provide the address to which a read or write operation will occur. addr[0] (lsb) must be sent to the liu first followed by addr[1] and so forth until all 8 address bits have been sampled by sclk. 6.1.4 r/w (sclk9) the next serial bit applied to the liu informs the micropro cessor that a read or write operation is desired. if the r/w bit is set to ?0?, the microprocessor is configured for a write operation. if the r/w bit is set to ?1?, the microprocessor is configured for a read operation. 6.1.5 dummy bits (sclk10 - sclk16) the next 7 sclk cycles are used as dummy bits. seve n bits were chosen so that the serial interface can easily be divided into three 8-bit words to be complia nt with standard serial interf ace devices. the state of these bits are ignored and can hold either ?0? or ?1? during both read and write operations. 6.1.6 data[7:0] (sclk17 - sclk24) the next 8 sclk cycles are used to provide the data to be written into the internal register chosen by the address bits. data[0] (lsb) must be sent to the liu firs t followed by data[1] and so forth until all 8 data bits have been sampled by sclk. once 24 sclk cycles have been completed, the liu holds the data until cs is pulled ?high? whereby, the serial microprocessor latc hes the data into the selected internal register. 6.1.7 8-bit serial data output description the serial data output is updated on the falling edge of sclk17 - sclk24 if r/w is set to ?1?. data[0] (lsb) is provided on sclk17 to the sdo pin first followed by data[1] and so forth until all 8 data bits have been updated. the sdo pin allows the us er to read the contents stored in individual registers by providing the desired address on the sdi pin during the read cycle.
xrt83sh38 43 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 f igure 34. t iming d iagram for the m icroprocessor s erial i nterface t able 13: m icroprocessor s erial i nterface t imings ( t a = 25 0 c, v dd =3.3v 5% and load = 10 p f) s ymbol p arameter m in . t yp . m ax u nits t 21 cs low to rising edge of sclk 5 ns t 22 sdi to rising edge of sclk 5 ns t 23 sdi to rising edge of sclk hold time 5 ns t 24 sclk "low" time 20 ns t 25 sclk "high" time 20 ns t 26 sclk period 40 ns t 28 cs inactive time 40 ns t 29 falling edge of sclk to sdo valid time 5 ns t 31 rising edge of cs to high z 5 ns sdi addr 6 r/w addr 7 cs sclk cs sclk sdi sdo d0 d1 d2 d7 t 21 t 22 t 23 t 24 t 25 t 26 t 28 t 29 t 31 don?t care (read mode) hi-z
xrt83sh38 44 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit 6.2 parallel microprocessor interface block the parallel microprocessor interface section supports communication between the local microprocessor (p) and the liu. the xrt83sh38 supports an intel asynchronous interface, motorola 68k asynchronous, and an intel/motorola interface. the microprocessor interface is selected by the state of the pts[1:0] input pins. selecting the microprocessor interface is shown in table 14 . the xrt83sh38 uses multipurpose pins to configure th e device appropriately. the local p configures the liu by writing data into specific addressable, on-chip read/write registers. the microprocessor interface provides the signals which are required for a general purpose microprocessor to read or write data into these registers. the microprocessor interface also supports polled and interrupt driven environments. a simplified block diagram of the microprocessor is shown in figure 35 . t able 14: s electing the m icroprocessor i nterface m ode pts[1:0] m icroprocessor m ode 0h (00) intel 68hc11, 8051, 80c188 (asynchronous) 1h (01) motorola 68k (asynchronous) 2h (10) intel x86 (synchronous) 3h (11) 860 motorola (synchronous) f igure 35. s implified b lock d iagram of the m icroprocessor i nterface b lock microprocessor interface wr_r/w rd_ds ale ptype [1:0] rdy reset pclk cs int addr[7:0] data[7:0]
xrt83sh38 45 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 6.3 the microprocessor interface block signals the liu may be configured into different operating modes and have its performance monitored by software through a standard microprocessor using data, address and control signals. these interface signals are described below in table 15 , table 16 , and table 17 . the microprocessor interface can be configured to operate in intel mode or motorola mode. when the microprocessor interface is operating in intel mode, some of the control signals function in a manner required by the intel 80xx family of microprocessors. likewise, when the microprocessor interface is operating in motorola m ode, then these control signals function in a manner as required by the motorola microprocessors. (for using a motorola 68k asynchronous processor, see figure 37 and table 19 ) table 15 lists and describes those microproce ssor interface signals whose role is constant across the two modes. table 16 describes the role of some of these signals when the microprocessor interface is operating in the intel mode. likewise, table 17 describes the role of these signals when the microprocessor interface is operating in the motorola power pc mode. t able 15: xrt83sh38 m icroprocessor i nterface s ignals that exhibit constant roles in both i ntel and m otorola m odes p in n ame t ype d escription pts[1:0] i microprocessor interface mode select input pins these three pins are used to specify the microprocessor interface mode. the relationship between the state of these three input pins, and the corresponding microprocessor mode is presented in table 14 . data[7:0] i/o bi-directional data bus for register "read" or "write" operations. addr[7:0] i eight-bit address bus inputs the xrt83sh38 liu microprocessor interface uses a direct address bus. this address bus is provided to permit the user to select an on-chip register for read/write access. cs i chip select input this active low signal selects the microprocessor interface of the xrt83sh38 liu and enables read/write operations with the on-chip register locations. t able 16: i ntel mode : m icroprocessor i nterface s ignals xrt83sh38 p in n ame i ntel e quivalent p in t ype d escription ale ale i address-latch enable: this active high signal is used to latch the contents on the address bus addr[7:0]. the contents of the address bus are latched into the addr[7:0] inputs on the falling edge of ale. rd _ds rd i read signal: this active low input functions as the read signal from the local p. when this pin is pulled ?low? (if cs is ?low?) the liu is informed that a read oper - ation has been requested and begins the process of the read cycle. wr _r/ w wr i write signal: this active low input functions as the write signal from the local p. when this pin is pulled ?low? (if cs is ?low?) the liu is informed that a write operation has been requested and begins the process of the write cycle. rdy rdy o ready output: this active low signal is provided by the liu device. it indicates that the current read or write cycle is complete, and the liu is waiting for the next command.
xrt83sh38 46 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit t able 17: m otorola m ode : m icroprocessor i nterface s ignals xrt83sh38 p in n ame m otorola e quivalent p in t ype d escription ale as i address strobe: this active high signal is used to latch the contents on the address bus addr[7:0]. the contents of the address bus are latched into the addr[7:0] inputs on the falling edge of ts. wr _r/ w r/ w i read/ write : this input pin from the local p is used to inform the liu whether a read or write operation has been requested. when this pin is pulled ?high?, ds will initia te a read operation. when this pin is pulled ?low?, ds will initia te a write operation. rd _ds ds i data strobe: this active low input functions as the read or write signal from the local p dependent on the state of r/ w . when ds is pulled ?low? (if cs is ?low?) the liu begins the read or write operation. rdy dtack o data transfer acknowledge: this active low signal is provided by the liu device. it indicates that the current read or write cycle is complete, and the liu is waiting for the next command.
xrt83sh38 47 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 6.4 intel mode programmed i/o access (asynchronous) if the liu is interfaced to an intel type p, then it should be configured to operate in the intel mode. intel type read and write operations are described below. intel mode read cycle whenever an intel-type p wishes to read the contents of a register, it should do the following. 1. place the address of the target register on the address bus input pins addr[7:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables further communication between the p and the liu microprocessor interface block. 3. toggle the ale input pin "high". this step enables the address bus input drivers, within the microproces - sor interface block of the liu. 4. the p should then toggle the ale pin "low". this step causes the liu to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 5. next, the p should indicate that this current bus cycle is a read operation by toggling the rd input pin "low". this action also enables the bi-direc tional data bus output drivers of the liu. 6. after the p toggles the read signal "low", the liu will toggle the rdy output pin "low". the liu does this in order to inform the p that the data is available to be read by the p, and that it is ready for the next com - mand. 7. after the p detects the rdy signal and has read the data, it can terminate the read cycle by toggling the rd input pin "high". n ote : ale can be tied ?high? if this signal is not available. the intel mode write cycle whenever an intel type p wishes to write a byte or word of data into a register within the liu, it should do the following. 1. place the address of the target register on the address bus input pins addr[7:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables further communication between the p and the liu microprocessor interface block. 3. toggle the ale input pin "high". this step enables the address bus input drivers, within the microproces - sor interface block of the liu. 4. the p should then toggle the ale pin "low". this step causes the liu to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 5. the p should then place the byte or word that it intends to write into the target register, on the bi-direc - tional data bus data[7:0]. 6. next, the p should indicate th at this current bus cycle is a write operation by toggling the wr input pin "low". this action also enables the bi-direc tional data bus input drivers of the liu. 7. after the p toggles the write sign al "low", the liu will toggle the rdy output pin "low". the liu does this in order to inform the p that the data has been written into the internal register location, and that it is ready for the next command. n ote : ale can be tied ?high? if this signal is not available. the intel read and write timing diagram is shown in figure 36 . the timing specifications are shown in table 18 .
xrt83sh38 48 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit f igure 36. i ntel p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations t able 18: i ntel m icroprocessor i nterface t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to rd assert 65 - ns t 2 rd assert to rdy assert - 90 ns na rd pulse width (t 2 ) 90 - ns t 3 cs falling edge to wr assert 65 - ns t 4 wr assert to rdy assert - 90 ns na wr pulse width (t 4 ) 90 - ns cs addr[10:0] ale = 1 data[7:0] rd wr rdy valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 4 t 2 t 3 valid address valid address
xrt83sh38 49 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 6.5 motorola mode programmed i/o access (asynchronous) if the liu is interfaced to a motorola type p, it should be configured to operate in the motorola mode. motorola type programmed i/o read and write operations are described below. motorola mode read cycle whenever a motorola type p wishes to read the contents of a register, it should do the following. 1. place the address of the target register on the address bus input pins addr[7:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables further communication between the p and the liu microprocessor interface block. 3. the p should then toggle the as pin "low". this st ep causes the liu to latch t he contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 4. next, the p should indicate that this current bus c ycle is a read operation by pulling the r/ w input pin "high". 5. toggle the ds input pin "low". this action enables the bi-directional data bus output drivers of the liu. 6. after the p toggles the ds signal "low", the liu will toggle the dtack output pin "low". the liu does this in order to inform the p that the data is available to be read by the p, and that it is ready for the next command. 7. after the p detects the dtack signal and has read the data, it can terminate the read cycle by toggling the ds input pin "high". motorola mode write cycle whenever a motorola type p wishes to write a byte or word of data into a register within the liu, it should do the following. 1. place the address of the target register on the address bus input pins addr[7:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables further communication between the p and the liu microprocessor interface block. 3. the p should then toggle the as pin "low". this st ep causes the liu to latch t he contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 4. next, the p should indicate that this current bus cycle is a write operation by pulling the r/ w input pin "low". 5. toggle the ds input pin "low". this action enables the bi-directional data bus output drivers of the liu. 6. after the p toggles the ds signal "low", the liu will toggle the dtack output pin "low". the liu does this in order to inform the p that the data has been writ ten into the internal register location, and that it is ready for the next command. 7. after the p detects the dtack signal and has read the data, it can terminate the read cycle by toggling the ds input pin "high". the motorola read and write timing diagram is shown in figure 37 . the timing specifications are shown in table 19 .
xrt83sh38 50 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit f igure 37. m otorola 68k p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations t able 19: m otorola 68k m icroprocessor i nterface t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to ds (pin rd _ds) assert 65 - ns t 2 ds assert to dtack assert - 90 ns na ds pulse width (t 2 ) 90 - ns t 3 cs falling edge to as (pin ale) falling edge 0 - ns cs addr[7:0] as data[7:0] rd _ds wr _r/w rdy _dtack valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 2 motorola asychronous mode valid address valid address t 3 t 3 t 1 t 2
xrt83sh38 51 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 register information t able 20: m icroprocessor r egister a ddress (addr[7:0]) r egister n umber a ddress (h ex ) f unction 0 - 15 0x00 - 0x0f channel 0 control registers 16 - 31 0x10 - 0x1f channel 1 control registers 32 - 47 0x20 - 0x2f channel 2 control registers 48 - 63 0x30 - 0x3f channel 3 control registers 64 - 79 0x40 - 0x4f channel 4 control registers 80 - 95 0x50 - 0x5f channel 5 control registers 96 - 111 0x60 - 0x6f channel 6 control registers 112 - 127 0x70 - 0x7f channel 7 control registers 128 - 142 0x80 - 0x8e global control registers applied to all 8 channels 192 0xc0 global control register applied to all 8 channels 143 - 253 0x8f - 0xfd r/w registers reserved for testing (except 0xc0h) 254 0xfe device "id" 255 0xff device "revision id" t able 21: m icroprocessor r egister c hannel d escription r eg addr t ype d7 d6 d5 d4 d3 d2 d1 d0 channel 0 control registers (0x00 - 0x0f) 0 0x00 r/w qrss/prbs prbs_rx/ tx rxon eqc4 eqc3 eqc2 eqc1 eqc0 1 0x01 r/w rxtsel txtsel tersel1 tersel0 jasel1 jasel0 jabw fifos 2 0x02 r/w invqrss txtest2 txtest1 txtest0 txon loop2 loop1 loop0 3 0x03 r/w reserved reserved codes rxres1 rxres0 insbpv insber reserved 4 0x04 r/w reserved dmoie flsie lcvi/ofe reserved aisdie rlosie qrpdie 5 0x05 ro reserved dmo fls lcv/of reserved ais rlos qrpd 6 0x06 rur reserved dmois flsis lcv/ofis reserved aisis rlosis qrpdis 7 0x07 ro reserved reserved reserved reserved reserved reserved reserved reserved 8 0x08 r/w reserved 1seg6 1seg5 1seg4 1seg3 1seg2 1seg1 1seg0 9 0x09 r/w reserved 2seg6 2seg5 2seg4 2seg3 2seg2 2seg1 2seg0 10 0x0a r/w reserved 3seg6 3seg5 3seg4 3seg3 3seg2 3seg1 3seg0 11 0x0b r/w reserved 4seg6 4seg5 4seg4 4seg3 4seg2 4seg1 4seg0 12 0x0c r/w reserved 5seg6 5seg5 5seg4 5seg3 5seg2 5seg1 5seg0 13 0x0d r/w reserved 6seg6 6seg5 6seg4 6seg3 6seg2 6seg1 6seg0 14 0x0e r/w reserved 7seg6 7seg5 7seg4 7seg3 7seg2 7seg1 7seg0
xrt83sh38 52 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit 15 0x0f r/w reserved 8seg6 8seg5 8seg4 8seg3 8seg2 8seg1 8seg0 channel (1 - 7) control registers (0x10 - 0x7f) see channel 0 global control registers for all 8 channels 128 0x80 r/w sr/dr ataos rclke tclke datap reserved gie sreset 129 0x81 r/w ovflo/lcv clksel2 clksel1 clksel0 mclkrate rxmute exlos ict 130 0x82 r/w txoncntl tercntl reserved reserved reserved reserved reserved reserved 140 0x8c r/w reserved reserved reserved reserved lcvch3 lcvch2 lcvch1 lcvch0 141 0x8d r/w reserved reserved reserved allrst allupdate bytesel chupdate chrst 142 0x8e ro lcvcnt7 lcvcnt6 lcvcnt5 lcvcnt4 lcvcnt3 lcvcnt2 lcvcnt1 lcvcnt0 192 0xc0 r/w reserved reserved reserved reserved reserved reserved reserved e1arben r/w registers reserved for testing (0x8f - 0xfd) except 0xc0h 254 0xfe ro device "id" 255 0xff ro device "revision id" t able 21: m icroprocessor r egister c hannel d escription r eg addr t ype d7 d6 d5 d4 d3 d2 d1 d0
xrt83sh38 53 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 t able 22: m icroprocessor r egister 0 x 00 h b it d escription c hannel 0-7 (0 x 00 h -0 x 70 h ) b it n ame f unction register type default value (hw reset) d7 qrss/ prbs qrss/prbs select bits these bits are used to select between qrss and prbs. 1 = qrss 0 = prbs r/w 0 d6 prbs_rx/ tx prbs receive/transmit select: this bit is used to select where the output of the prbs generator is directed if prbs generation is enabled. 0 = normal operation - prbs generator is output on ttip and tring if prbs generation is enabled. 1 = prbs generator is output on rpos; rneg is internally grounded, if prbs generation is enabled. n ote : if prbs generation is disabled, user should set this bit to ?0? for normal operation. r/w 0 d5 rxon receiver on/off upon power up, the receiver is powered off. rxon is used to turn the receiver on or off if the hardware pin rxon is pulled "high". if the hardware pin is pulled "low", all receivers are turned off. 0 = receiver is powered off 1 = receiver is powered on r/w 0 d4 d3 d2 d1 d0 eqc4 eqc3 eqc2 eqc1 eqc0 equalizer control bits the equalizer control bits are shown in table 23 below. r/w 0 0 0 0 0 pbrs generator tx ttip tring + - bit 6 = "0" pbrs generator rx rpos rneg + - bit 6 = "1"
xrt83sh38 54 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit t able 23: e qualizer c ontrol and t ransmit l ine b uild o ut eqc[4:0] t1/e1 m ode /r eceive s ensitivity t ransmit lbo c able c oding 0x08h t1 short haul/15db 0 to 133 feet (0.6db) 100 ? tp b8zs 0x09h t1 short haul/15db 133 to 266 feet (1.2db) 100 ? tp b8zs 0x0ah t1 short haul/15db 266 to 399 feet (1.8db) 100 ? tp b8zs 0x0bh t1 short haul/15db 399 to 533 feet (2.4db) 100 ? tp b8zs 0x0ch t1 short haul/15db 533 to 655 feet (3.0db) 100 ? tp b8zs 0x0dh t1 short haul/15db arbitrary pulse 100 ? tp b8zs 0x1ch e1 short haul/15db itu g.703 75 ? coax hdb3 0x1dh e1 short haul/15db itu g.703 120 ? tp hdb3 t able 24: m icroprocessor r egister 0 x 01 h b it d escription c hannel 0-7 (0 x 01 h -0 x 71 h ) b it n ame f unction register type default value (hw reset) d7 rxtsel receive termination select upon power up, the receiver is in "high" impedance. rxtsel is used to switch between the internal termination and "high" imped - ance. 0 = "high" impedance 1 = internal termination r/w 0 d6 txtsel transmit termination select upon power up, the transmitter is in "high" impedance. txtsel is used to switch between the internal termination and "high" imped - ance. 0 = "high" impedance 1 = internal termination r/w 0 d5 d4 tersel1 tersel0 receive line impedance select tersel[1:0] are used to select the line impedance for t1/j1/e1. 00 = 100 ? 01 = 110 ? 10 = 75 ? 11 = 120 ? r/w 0 0 d[3:2] jasel[1:0] jitter attenuator select jasel[1:0] are used to select the ji tter attenuator in the transmit or receive path. 00 = disabled 01 = transmit path 10 = receive path 11 = receive path r/w 0
xrt83sh38 55 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 d1 jabw jitter bandwidth (e1 mode only, t1 is permanently set to 3hz) the jitter bandwidth is a global setting that is applied to both the receiver and transmitter jitter attenuator. 0 = 10hz 1 = 1.5hz r/w 0 d0 fifos fifo depth select the fifo depth select is used to configure the part for a 32-bit or 64-bit fifo (within the jitter attenuator blocks). the delay of the fifo is equal to ? the fifo depth. this is a global setting that is applied to both the receiver and transmitter fifo. 0 = 32-bit 1 = 64-bit r/w 0 t able 25: m icroprocessor r egister 0 x 02 h b it d escription c hannel 0-7 (0 x 02 h -0 x 72 h ) b it n ame f unction register type default value (hw reset) d7 invqrss qrss inversion invqrss is used to invert the transmit qrss pattern set by the txtest[2:0] bits. by default, invqrss is disabled and the qrss will be transmitted with normal polarity. 0 = disabled 1 = enabled r/w 0 d6 d5 d4 txtest2 txtest1 txtest0 test code pattern txtest[2:0] are used to select a diagnostic test pattern to the line (transmit outputs). 0xx = no pattern 100 = tx qrss 101 = tx taos 110 = reserved 111 = reserved r/w 0 0 0 t able 24: m icroprocessor r egister 0 x 01 h b it d escription c hannel 0-7 (0 x 01 h -0 x 71 h ) b it n ame f unction register type default value (hw reset)
xrt83sh38 56 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit d3 txon transmit on/off upon power up, the transmitters are powered off. this bit is used to turn the transmitter for this channel on or off if the txon pin is pulled "high". if the txon pin is pulled "low", all 8 transmitters are powered off. 0 = transmitter is powered off 1 = transmitter is powered on r/w 0 d2 d1 d0 loop2 loop1 loop0 loopback diagnostic select loop[2:0] are used to select the loopback mode. 0xx = no loopback 100 = dual loopback 101 = analog loopback 110 = remote loopback 111 = digital loopback r/w 0 0 0 t able 26: m icroprocessor r egister 0 x 03 h b it d escription c hannel 0-7 (0 x 03 h -0 x 73 h ) b it n ame f unction register type default value (hw reset) d[7:6] reserved this register bit is not used. d5 codes encoding/decoding select (single rail mode only) 0 = hdb3 (e1), b8zs (t1) 1 = ami coding r/w 0 d4 d3 rxres1 rxres0 receive external fixed resistor rxres[1:0] are used to select the value for a high precision exter - nal resistor to improve return loss. 00 = none 01 = 240 ? 10 = 210 ? 11 = 150 ? r/w 0 0 d2 insbpv insert bipolar violation when this bit transitions from a "0" to a "1", a bipolar violation will be inserted in the transmitted qrss/prbs pattern. the state of this bit will be sampled on the rising edge of tclk. to ensure proper operation, it is recommended to write a "0" to this bit before writing a "1". r/w 0 t able 25: m icroprocessor r egister 0 x 02 h b it d escription c hannel 0-7 (0 x 02 h -0 x 72 h ) b it n ame f unction register type default value (hw reset)
xrt83sh38 57 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 d1 insber insert bit error when this bit transitions from a "0" to a "1", a bit error will be inserted in the transmitted qrss/prbs pattern. the state of this bit will be sampled on the rising edge of tclk. to ensure proper operation, it is recommended to write a "0" to this bit before writing a "1". r/w 0 d0 resereved t able 27: m icroprocessor r egister 0 x 04 h b it d escription c hannel 0-7(0 x 04 h -0 x 74 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used. d6 dmoie digital monitor output interrupt enable 0 = masks the dmo function 1 = enables interrupt generation r/w 0 d5 flsie fifo limit status interrupt enable 0 = masks the fls function 1 = enables interrupt generation r/w 0 d4 lcv/ofie line code violation / counter overflow interrupt enable 0 = masks the lcv/of function 1 = enables interrupt generation r/w 0 d3 reserved this register bit is not used. d2 aisie alarm indication signal interrupt enable 0 = masks the ais function 1 = enables interrupt generation r/w 0 d1 rlosie receiver loss of signal interrupt enable 0 = masks the rlos function 1 = enables interrupt generation r/w 0 d0 qrpdie quasi random signal source interrupt enable 0 = masks the qrpd function 1 = enables interrupt generation r/w 0 t able 26: m icroprocessor r egister 0 x 03 h b it d escription c hannel 0-7 (0 x 03 h -0 x 73 h ) b it n ame f unction register type default value (hw reset)
xrt83sh38 58 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit n ote : the gie bit in the global register 0x80h must be set to "1 " in addition to the individual register bits to enable the interrupt pin. t able 28: m icroprocessor r egister 0 x 05 h b it d escription c hannel 0-7 (0 x 05 h -0 x 75 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used. d6 dmo digital monitor output the digital monitor output is always active regardless if the inter - rupt generation is disabled. this bit indicates the dmo activity. an interrupt will not occur unless the dmoie is set to "1" in the chan - nel register 0x04h and gie is set to "1" in the global register 0x80h. 0 = no alarm 1 = transmit output driver has failures ro 0 d5 fls fifo limit status the fifo limit status is always active regardless if the interrupt generation is disabled. this bit indicates whether the rd/wr pointers are within 3-bits. an interrupt will not occur unless the flsie is set to "1" in the channel register 0x04h and gie is set to "1" in the global register 0x80h. 0 = no alarm 1 = rd/wr fifo pointers are within 3-bits ro 0 d4 lcv/of line code violation / counter overflow this bit serves a dual purpose. by default, this bit monitors the line code violation activity. however, if bit 7 in register 0x81h is set to a "1", this bit monitors the overflow status of the internal lcv counter. an interrupt will not occur unless the lcv/ofie is set to "1" in the channel register 0x04h and gie is set to "1" in the global register 0x80h. 0 = no alarm 1 = a line code violation, bipolar violation, or excessive zeros has occurred ro 0 d3 reserved this register bit is not used. d2 aisd alarm indication signal the alarm indication signal detection is always active regardless if the interrupt generation is disabled. this bit indicates the ais activity. an interrupt will not occur unless the aisie is set to "1" in the channel register 0x04h and gie is set to "1" in the global regis - ter 0x80h. 0 = no alarm 1 = an all ones signal is detected ro 0
xrt83sh38 59 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 d1 rlos receiver loss of signal the receiver loss of signal detection is always active regardless if the interrupt generation is disabled. this bit indicates the rlos activity. an interrupt will not occur unless the rlosie is set to "1" in the channel register 0x04h and gie is set to "1" in the global register 0x80h. 0 = no alarm 1 = an rlos condition is present ro 0 d0 qrpd quasi random pattern detection the quasi random pattern detection is always active regardless if the interrupt generation is disabled. this bit indicates that a qrpd has been detected. an interrupt will not occur unless the qrpdie is set to "1" in the channel register 0x04h and gie is set to "1" in the global register 0x80h. 0 = no alarm 1 = a qrp is detected ro 0 t able 29: m icroprocessor r egister 0 x 06 h b it d escription c hannel 0-7 (0 x 06 h -0 x 76 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used. d6 dmois digital monitor output status 0 = no change 1 = change in status occurred rur 0 d5 flsis fifo limit status 0 = no change 1 = change in status occurred rur 0 d4 lcv/ofis line code violation / overflow status 0 = no change 1 = change in status occurred rur 0 d3 reserved this register bit is not used. d2 aisdis alarm indication signal status 0 = no change 1 = change in status occurred rur 0 n ote : the gie bit in the global register 0x80h must be set to "1 " in addition to the individual register bits to enable the interrupt pin. t able 28: m icroprocessor r egister 0 x 05 h b it d escription c hannel 0-7 (0 x 05 h -0 x 75 h ) b it n ame f unction register type default value (hw reset)
xrt83sh38 60 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit n ote : any change in status will generate an interrupt (if enabled in channel register 0x04h and gie is set to "1" in the global register 0x80h). the status registers are reset upon read (rur). d1 rlosis receiver loss of signal status 0 = no change 1 = change in status occurred rur 0 d0 qrpdis quasi random pattern detection status 0 = no change 1 = change in status occurred rur 0 t able 30: m icroprocessor r egister 0 x 08 h b it d escription c hannel 0-7 (0 x 08 h -0 x 78 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d6 d5 d4 d3 d2 d1 d0 1seg6 1seg5 1seg4 1seg3 1seg2 1seg1 1seg0 arbitrary pulse generation the transmit output pulse is divided into 8 individual segments. this register is used to program the first segment which corre - sponds to the overshoot of the pulse amplitude. there are four segments for the top portion of the pulse and four segments for the bottom portion of the pulse. segment number 5 corresponds to the undershoot of the pulse. the msb of each segment is the sign bit. bit 6 = 0 = negative direction bit 6 = 1 = positive direction r/w 0 0 0 0 0 0 0 t able 31: m icroprocessor r egister 0 x 09 h b it d escription c hannel 0-7 (0 x 09 h -0 x 79 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 2seg[6:0] segment number two, same description as register 0x08h r/w t able 29: m icroprocessor r egister 0 x 06 h b it d escription c hannel 0-7 (0 x 06 h -0 x 76 h ) b it n ame f unction register type default value (hw reset)
xrt83sh38 61 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 t able 32: m icroprocessor r egister 0 x 0a h b it d escription c hannel 0-7 (0 x 0a h -0 x 7a h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 3seg[6:0] segment number three, same description as register 0x08h r/w t able 33: m icroprocessor r egister 0 x 0b h b it d escription c hannel 0-7 (0 x 0b h -0 x 7b h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 4seg[6:0] segment number four, same description as register 0x08h r/w t able 34: m icroprocessor r egister 0 x 0c h b it d escription c hannel 0-7 (0 x 0c h -0 x 7c h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 5seg[6:0] segment number five, same description as register 0x08h r/w t able 35: m icroprocessor r egister 0 x 0d h b it d escription c hannel 0-7 (0 x 0d h -0 x 7d h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 6seg[6:0] segment number six, same description as register 0x08h r/w
xrt83sh38 62 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit t able 36: m icroprocessor r egister 0 x 0e h b it d escription c hannel 0-7 (0 x 0e h -0 x 7e h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 7seg[6:0] segment number seven, same description as register 0x08h r/w t able 37: m icroprocessor r egister 0 x 0f h b it d escription c hannel 0-7 (0 x 0f h -0 x 7f h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 8seg[6:0] segment number eight, same description as register 0x08h r/w
xrt83sh38 63 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 t able 38: m icroprocessor r egister 0 x 80 h , b it d escription r egister a ddress 0 x 80 h n ame f unction r egister t ype r eset v alue b it # d7 sr/ dr single-rail/dual-rail select: writing a ?1? to this bit configures all 8 channels in the xrt83sh38 to operate in the single-rail mode. writing a ?0? configures the xrt83sh38 to operate in dual-rail mode. r/w 0 d6 ataos automatic transmit all ones upon rlos: writing a ?1? to this bit enables the automatic transmission of all "ones" data to the line for the channel that detects an rlos condition. writing a ?0? disables this feature. r/w 0 d5 rclke receive clock edge: writing a ?1? to this bit selects receive output data of all channels to be updated on the negative edge of rclk. wring a ?0? selects data to be updated on the positive edge of rclk. r/w 0 d4 tclke transmit clock edge: writing a ?0? to this bit selects transmit data at tpos_n/tdata_n and tneg_n/codes_n of all channels to be sampled on the falling edge of tclk_n. writing a ?1? selects the rising edge of the tclk_n for sam - pling. r/w 0 d3 datap data polarity: writing a ?0? to this bit selects transmit input and receive output data of all channels to be active ?high?. writing a ?1? selects an active ?low? state. r/w 0 d2 reserved 0 d1 gie global interr upt enable: writing a ?1? to this bit globally enables interrupt generation for all channels. writing a ?0? disables interrupt generation. r/w 0 d0 sreset software reset p registers: writing a ?1? to this bit longer than 10s initiates a device reset through the microprocessor interface. all internal circuits are placed in the reset state with this bit set to a ?1? except the microprocessor register bits. r/w 0
xrt83sh38 64 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit clock select register the input clock source is used to generate all the ne cessary clock references internally to the liu. the microprocessor timing is derived from a pll output whic h is chosen by programming the clock select bits and the master clock rate in register 0x 81h. therefore, if the clock select ion bits or the mclrate bit are being programmed, the freq uency of the pll ou tput will be adjusted ac cordingly. during th is adjustment, it is important to "not" write to any other bit location within the same register while sele cting the input/output clock frequency. for best results, register 0x81h can be br oken down into two sub-register s with the msb being bits d[7:3] and the lsb being bits d[2:0] as shown in figure 38 . note: bit d[7] is a reserved bit. f igure 38. r egister 0 x 81 h s ub r egisters programming examples: example 1: changing bits d[7:3] if bits d[7:3] are the only values with in the register that will change in a write process, th e microprocessor only needs to initiate one write operation. example 2: changing bits d[2:0] if bits d[2:0] are the only values with in the register that will change in a write process, th e microprocessor only needs to initiate one write operation. example 3: changing bits within the msb and lsb in this scenario, one must initiate two write operatio ns such that the msb and lsb do not change within one write cycle. it is recommended that th e msb and lsb be treated as two in dependent sub-registers. one can either change the clock selection (msb) and then change bits d[2:0] (lsb) on the second write, or vice- versa. no order or sequence is necessary. d0 d1 d2 d3 d4 d5 d6 d7 msb lsb clock selection bits exlos, ict
xrt83sh38 65 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 t able 39: m icroprocessor r egister 0 x 81 h , b it d escription r egister a ddress 0 x 81 h n ame f unction r egister t ype r eset v alue b it # d7 reserved r/w 0 d6 clksel2 clock select inputs for master clock synthesizer bit 2: in host mode, clksel[2:0] are inpu t signals to a programma - ble frequency synthesizer that can be used to generate a mas - ter clock from an external accura te clock source according to the following table; in hardware mode, the state of these signals are ignored and the master frequency pll is controlled by the corresponding hardware pins. r/w 0 d5 clksel1 clock select inputs for master clock synthesizer bit 1: see description of bit d6 for function of this bit. r/w 0 d4 clksel0 clock select inputs for master clock synthesizer bit 0: see description of bit d6 for function of this bit. r/w 0 d3 mclkrate master clock rate select: the state of this bit programs the master clock synthesizer to generate the t1/j1 or e1 clock. the master clock synthesizer w ill generate the e1 clock when mclkrate = ?0?, and the t1/j1 clock when mclkrate = ?1?. r/w 0 d2 rxmute receive output mute: writing a ?1? to this bit, mutes receive outputs at rpos/rdata and rneg/lcv pins to a ?0? state for any channel that detects an rlos condition. n ote : rclk is not muted. r/w 0 2048 2048 2048 1544 mclke1 khz 8 16 16 56 8 56 64 64 128 256 256 128 2048 2048 1544 1544 mclkt1 khz 1544 x x x 1544 x x x x x x x 2048 1544 2048 clkout/ khz 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 0 0 1 1 clksel0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 0 0 clksel1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 clksel2 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 1544 2048 x x 2048 1544 0 1 0 1 mclkrate 1 0 1 0 0 1 0 1 1 0 1 0 0 1
xrt83sh38 66 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit d1 exlos extended los: writing a ?1? to this bit extends the number of zeros at the receive input of each channel before rlos is declared to 4096 bits. writing a ?0? reverts to the normal mode (175+75 bits for t1 and 32 bits for e1). r/w 0 d0 ict in-circuit-testing: writing a ?1? to this bit configures all the output pins of the chip in high impedance mode for in-circuit- testing. setting the ict bit to ?1? is equivalent to connecting the hardware ict pin 88 to ground. r/w 0 t able 40: m icroprocessor r egister 0 x 82 h b it d escription g lobal r egister (0 x 82 h ) b it n ame f unction register type default value (hw reset) d7 txoncntl transmit on control 0 = control of receive termination is set; if in hardware mode, by rxtsel pins if in host mode by the rxtsel bit 0 = control of transmitter is set ; if hardware mode, by txon pin if host mode, by txon bit 1 = control of transmitter on, is determined by the individual chan - nel txon bits r/w 0 d6 tercntl receive termination select control this bit sets the liu to control the rxtsel function with either the individual channel register bit or the global hardware pin. 0 = control of the receive terminat ion is set tby hardware-host bit or hardware pin and individual software 1 = control of the receive termination is set to the hardware pin r/w 0 d[5:0] reserved these register bits are not used t able 39: m icroprocessor r egister 0 x 81 h , b it d escription
xrt83sh38 67 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 t able 41: m icroprocessor r egister 0 x 8c h b it d escription g lobal r egister (0 x 8c h ) b it n ame f unction register type default value (hw reset) d[7:4] reserved tese register bits are not used r/w 0 d3 d2 d1 d0 lcvch3 lcvch2 lcvch1 lcvch0 line code violation counter select these bits are used to select which channel is to be addressed for reading the contents in register 0x8eh. it is also used to address the counter for a given channel when performing an update or reset on a per channel basis. by default, channel 0 is selected. 0000 = none 0001 = channel 0 0010 = channel 1 0011 = channel 2 0100 = channel 3 0101 = channel 4 0110 = channel 5 0111 = channel 6 1000 = channel 7 r/w 0 0 0 0 t able 42: m icroprocessor r egister 0 x 8d h b it d escription g lobal r egister (0 x 8d h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used r/w 0 d6 reserved this register bit is not used r/w 0 d5 reserved this register bit is not used r/w 0 d4 allrst lcv counter reset for all channels this bit is used to reset all internal lcv counters to their default state 0000h. this bit must be set to "1" for 1 s. 0 = normal operation 1 = resets all counters r/w 0 d3 allupdate lcv counter update for all channels this bit is used to latch the contents of all 8 counters into holding registers so that the value of each counter can be read. the chan - nel is addressed by using bits d[3:0] in register 0x8ch. 0 = normal operation 1 = updates all counters r/w 0
xrt83sh38 68 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit d2 bytesel lcv counter byte select this bit is used to select the msb or lsb for reading the contents of the lcv counter for a given channel. the channel is addressed by using bits d[3:0] in register 0x8ch. by default, the lsb byte is selected. 0 = low byte 1 = high byte r/w 0 d1 chupdate lcv counter update per channel this bit is used to latch the contents of the counter for a given channel into a holding register so that the value of the counter can be read. the channel is addressed by using bits d[3:0] in register 0x8ch. 0 = normal operation 1 = updates the selected channel r/w 0 d0 chreset lcv counter reset per channel this bit is used to reset the lcv counter of a given channel to its default state 0000h. the channel is addressed by using bits d[3:0] in register 0x8ch. this bit must be set to "1" for 1 s. 0 = normal operation 1 = resets the selected channel r/w 0 t able 43: m icroprocessor r egister 0 x 8e h b it d escription g lobal r egister (0 x 8e h ) b it n ame f unction register type default value (hw reset) d7 d6 d5 d4 d3 d2 d1 d0 lcvcnt7 lcvcnt6 lcvcnt5 lcvcnt4 lcvcnt3 lcvcnt2 lcvcnt1 lcvcnt0 line code violation byte contents these bits contain the lcv counter contents of the byte selected by bit d2 in register 0x8dh for a given channel. the channel is addressed by using bits d[3:0] in register 0x8ch. by default, the contents contain the lsb, however no channel is selected.. r/w 0 0 0 0 0 0 0 0 t able 42: m icroprocessor r egister 0 x 8d h b it d escription g lobal r egister (0 x 8d h ) b it n ame f unction register type default value (hw reset)
xrt83sh38 69 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 t able 44: m icroprocessor r egister 0 x c0 h b it d escription g lobal r egister (0 x c0 h ) b it n ame f unction register type default value (hw reset) d[7:1] reserved these register bits are not used. r/w 0 d0 e1arben e1 arbitrary pulse enable this bit is used to enable the ar bitrary pulse generators for shap - ing the transmit pulse shape when e1 mode is selected. if this bit is set to "1", all 8 channels will be configured for the arbitrary mode. however, each channel is individually controlled by pro - gramming the channel registers 0xn8 through 0xnf, where n is the number of the channel. "0" = disabled (normal e1 pulse shape itu g.703) "1" = arbitrary pulse enabled r/w 0 t able 45: m icroprocessor r egister 0 x fe h b it d escription d evice "id" r egister (0 x fe h ) b it n ame f unction register type default value (hw reset) d7 d6 d5 d4 d3 d2 d1 d0 device "id" the device "id" of the xrt83sh38 short haul liu is 0xf5h. along with the revision "id", the device "id" is used to enable software to identify the silicon adding flex ibility for system control and debug. ro 1 1 1 1 0 1 0 1 t able 46: m icroprocessor r egister 0 x ff h b it d escription r evision "id" r egister (0 x ff h ) b it n ame f unction register type default value (hw reset) d7 d6 d5 d4 d3 d2 d1 d0 revision "id" the revision "id" of the xrt83sh38 liu is used to enable soft - ware to identify which revision of silicon is currently being tested. the revision "id" for the first revision of silicon will be 0x01h. ro 0 0 0 0 0 0 0 1
xrt83sh38 70 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit electrical characteristics n ote : input leakage current excludes pins that are internally pulled "low" or "high" t able 47: a bsolute m aximum r atings storage temperature -65c to +150c operating temperature -40c to +85c supply voltage -0.5v to +3.8v vin -0.5v to +5.5v t able 48: dc d igital i nput and o utput e lectrical c haracteristics vdd=3.3v 5%, t a =25c, u nless o therwise s pecified p arameter s ymbol m in t yp m ax u nits power supply voltage vdd 3.13 3.3 3.46 v input high voltage v ih 2.0 - 5.0 v input low voltage v il -0.5 - 0.8 v output high voltage ioh=2.0ma v oh 2.4 - v output low voltage iol=2.0ma v ol - - 0.4 v input leakage current i l - - 10 a input capacitance c i - 5.0 pf output lead capacitance c l - - 25 pf t able 49: ac e lectrical c haracteristics vdd=3.3v 5%, t a =25c, u nless o therwise s pecified p arameter s ymbol m in t yp m ax u nits mclkin clock duty cycle 40 - 60 % mclkin clock tolerance - 50 - ppm
xrt83sh38 71 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 t able 50: p ower c onsumption vdd=3.3v 5%, t a =25c, u nless o therwise s pecified m ode s upply v oltage i mpedance r eceiver t ransmitter t yp m ax u nit t est c ondition e1 3.3v 75 ? 1:1 1:2 1.059 1.422 - w 50% ones 100% ones e1 3.3v 120 ? 1:1 1:2 0.974 1.264 - w 50% ones 100% ones t1 3.3v 100 ? 1:1 1:2 1.465 1.904 - w 50% ones 100% ones t able 51: e1 r eceiver e lectrical c haracteristics vdd=3.3v 5%, t a =25c, u nless o therwise s pecified p arameter m in t yp m ax u nit t est c ondition receiver loss of signal number of consecutive zeros before rlos is declared input signal level at rlos rlos clear - 15 12.5 32 24 - - - - db % ones cable attenuation @ 1024khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 11 - - db with nominal pulse amplitude of 3.0v for 120 ? and 2.37v for 75 ? with -18db interference signal added. input impedance - 13 - k ? input jitter tolerance 1hz 10khz - 100khz 37 0.2 - - - - ui p-p ui p-p itu-g.823 recovered clock jitter transfer corner frequency peaking amplitude - - 36 - - -0.5 khz db itu-g.736 jitter attenuator corner fre - quency jabw = 0 jabw = 1 - - 10 1.5 - - hz hz itu-g.736 return loss 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz 14 20 16 - - - - - - db db db itu-g.703
xrt83sh38 72 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit t able 52: t1 r eceiver e lectrical c haracteristics vdd=3.3v 5%, t a =25c, u nless o therwise s pecified p arameter m in t yp m ax u nit t est c ondition receiver loss of signal number of consecutive zeros before rlos is declared input signal level at rlos rlos clear 160 15 12.5 175 24 - 190 - - db % ones cable attenuation @ 772khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 12 - - db with nominal pulse amplitude of 3.0v for 100 ? termination. input impedance - 13 - k ? input jitter tolerance 1hz 10khz - 100khz 138 0.4 - - - - ui p-p ui p-p at&t pub 62411 recovered clock jitter transfer corner frequency peaking amplitude - - 9.8 - - 0.1 khz db tr-tsy-000499 jitter attenuator corner fre - quency - 6 - hz at&t pub 62411 return loss 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz - - - 20 25 25 - - - db db db
xrt83sh38 73 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 t able 53: e1 t ransmitter e lectrical c haracteristics vdd=3.3v 5%, t a =25c, u nless o therwise s pecified p arameter m in t yp m ax u nit t est c ondition ami output pulse amplitude 75 ? 120 ? 2.13 2.70 2.37 3.00 2.60 3.30 v v 1:2 transformer output pulse width 224 244 264 ns output pulse width ratio 0.95 - 1.05 itu-g.703 output pulse amplitude ratio 0.95 - 1.05 itu-g.703 jitter added by the transmitter output - 0.025 0.05 ui p-p broad band with jitter free tclk applied to the input. output return loss 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz 8 14 10 - - - - - - db db db etsi 300 166, chptt t able 54: t1 t ransmitter e lectrical c haracteristics vdd=3.3v 5%, t a =25c, u nless o therwise s pecified p arameter m in t yp m ax u nit t est c ondition ami output pulse amplitude 2.4 3.0 3.6 v 1:2 transformer measured at dsx-1 output pulse width 338 350 362 ns ansi t1.102 output pulse width imbalance - - 20 ansi t1.102 output pulse amplitude imbal - ance - - 200 mv ansi t1.102 jitter added by the transmitter output - 0.025 0.05 ui p-p broad band with jitter free tclk applied to the input. output return loss 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz - - - 15 15 15 - - - db db db
xrt83sh38 74 rev. 1.0.7 8-channel t1/e1/j1 short-haul line interface unit package dimensions 225 b all p lastic b all g rid a rray (b ottom v iew ) (19.0 x 19.0 x 1.0mm) 1 2 4 3 7 86 5 17 16 14 15 12 13 11 10 9 18 a b c d e f g h j k l m n p r t u v d d1 d d1 a1 feature / mark d2 a a1 a2 a3 e b (a1 corner feature is mfger option) seating plane symbol min max min max a 0.049 0.096 1.24 2.45 a1 0.016 0.024 0.40 0.60 a2 0.013 0.024 0.32 0.60 a3 0.020 0.048 0.52 1.22 d 0.740 0.756 18.80 19.20 d1 0.669 bsc 17.00 bsc d2 0.665 0.669 16.90 17.00 b 0.020 0.028 0.50 0.70 e 0.039 bsc 1.00 bsc inches millimeters note: the control dimension is in millimeter.
75 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and sche dules contained here in ar e only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2006 exar corporation datasheet september 2006. reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xrt83sh38 8-channel t1/e1/j1 short-haul line interface unit rev. 1.0.7 ordering information revisions p art n umber p ackage o perating t emperature r ange xrt83sh38ib 225 ball bga -40 c to +85 c r evision # d ate d escription 1.0.0 12/15/05 release to production 1.0.1 01/04/05 removed tratio, gain cont rol section, text edits. 1.0.2 4/19/06 corrected referenced hex bits in register 0x05 bit4, lcv/of. (0xe5h to 0x81h & 0xe0h to 0x80h.) changed logo format. 1.0.3 5/30/06 replaced tbd in power consumption table with typical numbers. 1.0.4 7/17/06 pin number correction, changed sdo pin number from a6 to r7 1.0.5 08/0306 added note to figure 33, (for applications without a free running sclk, a minimum of 1 sclk pulse must be applied when cs is "high", befor cs is pulled "low". 1.0.6 08/11/06 added timing diagram and specs for the up serial interface. 1.0.7 09/08/06 modified table 23, deleted 0x0eh to 0x13h and 0x1eh to 0x1fh values for eqc[4:0].

▲Up To Search▲

Price & Availability of XRT83SH380609

	To Download XRT83SH380609 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .